Intel Corporation

James S Griffith

Shantanu R Gupta

Glenn J Hinton

Andrew F Glew

David B Papworth

Michael A Fetterman

Robert P Colwell

A method and apparatus for dynamically allocating entries of microprocessor resources to particular instructions in an efficient manner to efficiently utilize buffer size and resources. The pipelined and superscalar microprocessor is capable of speculatively executing instructions and also out-of-order processing. Resources within the microprocessor include a store buffer, a load buffer, a reorder buffer and a reservation station. The reorder buffer contains a larger set of physical registers and also contains information related to speculative instructions and the reservation station comprises information related to instructions pending execution. The load buffer is only allocated to load instructions and is valid for an instruction from allocation pipestage to instruction retirement. The store buffer is only allocated to store instructions and is valid for an instruction from allocation to store performance. The reservation station is allocated to most instructions and is valid for an instruction from allocation to instruction dispatch. The reorder buffer is allocated to all instructions and is valid for a given instruction from allocation to retirement. The load buffer, store buffer, and reorder buffer are sequentially allocated while the reservation station is not. Resource allocation is performed dynamically (as needed by the operation) rather than as a full set of resources attached to each operation. Using the above allocation scheme, efficient usage of the microprocessor resources is accomplished.

Method and apparatus for dynamic allocation of multiple buffers in a

A method and apparatus for binding instructions to dispatch ports in a reservation station includes a counter mechanism and a port identifier. The counter mechanism maintains a count of instructions which are pending dispatch from at least one of the dispatch ports. The port identifier receives an instruction and identifies to which of the dispatch ports the instruction is to be bound, based on the count of instructions maintained by the counter mechanism.

Method and apparatus for binding instructions to dispatch ports of a

A two cycle pipelined method and apparatus for allocating a number of vacant entries of a buffer resource and generating a set of enable vectors based thereon for a set of issued instructions. The procedure for determining the vacant entries is spread across two pipestages (clock cycles) of a pipelined superscalar processor. For each pipestage, the system receives information from the previous pipestage as to which entries were eligible for allocation but have not yet received instruction information as well as a set of speculative stall signals. For each pipestage, the reservation station informs the system as to which entries are vacant according to the reservation station's knowledge at that time; this is a preliminary deallocation vector. For each pipestage, the system also receives a list of the instructions for allocation to the reservation station for that cycle. The system formulates a modified deallocation vector from the above information by masking bits of the preliminary deallocation vector and also performs stall checking in the event there are not enough vacant entries. The system interrogates the modified deallocation vector to locate the vacancies within the reservation station for storage of instruction information associated with several issued operations. A general static and dynamic approach are disclosed for performing the vacant entry identification at high speed within a single clock cycle.

Apparatus and method for entry allocation for a buffer resource

A method and apparatus for searching for a pattern of values indicating vacancy within a reservation station. The present invention includes a method and apparatus for search a deallocation vector of an instruction scheduler in order to locate, within one clock cycle, a pattern of the first vacancies within the instruction scheduler for storage of instruction information associated with several microprocessor instructions. The present invention advantageously locates four vacant entries of the deallocation vector which specify the first four vacancies within a reservation station of the instruction scheduler and may be utilized to locate the first four vacant entries as well. The present invention performs the above processing utilizing high speed parallel processing methods so that the entire searching, reporting and updating functions, with regard to the deallocation vector, can be completed within one clock cycle. Two embodiments of the present invention, a static and a dynamic embodiment, are presented. Advantageously utilizing the present invention, a multi-instruction processing microprocessor may quickly and efficiently, within one clock cycle, schedule up to four instructions from the instruction decoder to the execution units of the microprocessor.

Entry allocation apparatus and method of same

A method and apparatus for allocating a number of vacant entries of a buffer resource and generating a set of enable vectors based thereon for a set of issued instructions. A deallocation vector of a reservation station is searched in order to locate, within one clock cycle, the vacancies within the reservation station for storage of instruction information associated with several issued operations. Vacancies are indicated by bits of the deallocation vector. A general static and dynamic approach are disclosed for performing the vacant entry identification at high speed within a single clock cycle. Alternate embodiments are disclosed, based on the general approach, that divide the deallocation vector into separate portions (consecutive bits or interleaved) and process each portion based on the general approaches. Rotating priority reference points within the deallocation vector may be used to vary the starting point for vacancy location. Further, the vacancy search can be limited to finding only consecutive vacancies. A superscalar microprocessor using the above may, within one clock cycle, schedule a group of instructions from the instruction decoder to the reservation station for subsequent execution.

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Aloha, OR, United States of America

James S Griffith