Cirrus Logic Inc.

Motorola Corporation

Other

Crystal Semiconductor Corporation

James S Divine

Jeffrey A Niehaus

Raghunath Krishna Rao

Miroslav V Dokic

Zheng Luo

Charles F Studor

John Robert Pacourek

Terry Ritchie

Baker P Scott

Michael I Catherwood

Baker Scott, Iii

Protective headgear includes, for example, a headgear body that is wearable on a head of a baseball umpire. At least one sensor is configured to generate imaging data that includes a batter in proximity to home plate. A processor analyzes the imaging data to determine a strike zone of the batter and to generate augmented reality data in response thereto. A display device generates a heads up display of the strike zone that is viewable to the baseball umpire during a pitch to the batter, based on the augmented reality data. Other embodiments are disclosed.

Protective headgear with display and methods for use therewith

A method of operating shared memory in a multiple processor system. A token is by default maintained with a first processor, the token enabling access to shared memory. A determination is made that a second processor requires access to shared memory. A determination is also made as to whether the first processor is accessing to the shared memory. The token is transferred the second processor if the first processor is not accessing the shared memory. The second processor accesses the shared memory with the token.

Accessing shared memory using token bit held by default by a single processor

A method of processing a stream of audio information received by a multiple processor audio decoder. Processing operations are performed by a first processor on the stream of audio information to produce at set of results. The first processor writes the set of results into a shared memory and a flag is set indicating that the results are ready. In response to the flag, a second processor reads the results from shared memory. When the results have been read from shared memory, the second processor sends a command to the first processor. The first processor then clears the flag.

Methods for processing audio information in a multiple processor audio decoder

A method of exchanging messages between first and second processors. A pending flag in a first register is polled by the first processor and if the flag is in a first selected logic state, a message is written into a second register with the first processor. The pending flag is set to a second selected logic state with the first processor and an interrupt to the second processor is generated. The message is read from the second register with the second processor when the pending flag is in the second logic state. The pending flag set to the first logic state with the second processor.

Interprocessor communication circuitry and methods

A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is interrupted. An input ready bit is set and first word from in the register is read with the target processor. A number of words in the sequence to follow the first word determined from the first word. A word counter is set and the input ready bit is cleared with the target processor. The target processor is returned to main code execution.

Methods for debugging a multiprocessor system

An audio decoder 100 for operating on a received compressed audio data stream compressed using an algorithm employing transform encoding and a bit allocation routine. A first processor 200 performs a first set of operations on the received compressed audio data stream including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating a bit allocation, and passing frequency domain coefficients to shared memory. A second digital signal processor 100b performs a second set of operations on data passed from the first digital signal processor to shared memory including performing inverse transform operations on the data passed from the first digital signal processor.

Dual processor digital audio decoder with shared memory data transfer

A message is transferred from external device through a first processor and from the first processor to a second processor. A check is made that the message passed to the second processor without error. The message is interpreted by a selected one of the first and second processors. Boot operations are performed by the selected processor in response to the interpretation of the message.

Methods for booting a multiprocessor system

A method of generating zero detect flag at the output of an adder adding a first vector and a second vector to generate a third vector. A fourth vector is generated from the third vector a carry propagation vector and a carry generation vector. A fifth vector generated using an incremented third vector and an incremented carry propagation vector. A sixth vector generated from the fourth vector and the fifth vector. The bits of the sixth vector bitwise added to obtain the zero detection flag.

Zero detection circuitry and methods

A voltage controlled oscillator with bias current calibration includes a voltage controlled oscillator 1504. A tuning current source 1510 is coupled to oscillator 1504 in parallel with bias current source 1512 for providing a tuning current to oscillator 1504. A selected control voltage is provided by oscillator 1504 for setting an oscillator output frequency. Control circuitry 1513, 1514 allows adjusting of the tuning current source to optimize bias current.

Bias current calibration of voltage controlled oscillator

An extensible central processing unit (CPU) (12 or 12'). By modifying the architecture of a new or prior art CPU, a new or prior art CPU can be made extensible so that new instructions can be added in a simple and cost effective manner to meet differing customer needs. The term 'extensible' in regard to a CPU is used to mean that new instructions can be added to the CPU simply by adding certain designated circuitry, without the need to significantly change the existing CPU circuitry. In some embodiments, the additional designated circuitry may include control circuitry in the form of CPU control extension circuitry (52 or 152). In some embodiments, the additional circuitry may include non-control circuitry in the form of execution unit extension circuitry (153).

Extensible central processing unit

A data processing system providing an extensible register and method thereof. A new CPU has an extensible index register. The new CPU is object code compatible with the old CPU having an 8-bit index register, yet the index register of the new CPU can be effectively extended to 16 bits when new instructions are used. As a consequence, the user is able to make the choice between using assembly code software written for the old CPU and having the functionality of an 8-bit index register, or writing new assembly code software for the new CPU and having the functionality of a 16-bit index register.

Method for providing an extensible register in the first and second data

A data processing system (10) executes a branch instruction in a straight line microcode sequence. During execution of the instruction, a control unit (56) is provided to decode the instruction to provide a plurality of control signals and to determine a data value with which to test a condition of the instruction. A constants generation circuit (222) generates a mask value in response to the plurality of control signals. An arithmetic logic unit (224) logically combines the mask value with the data value to produce a masked value. A zero detect circuit (246) subsequently tests the masked value to determine if it is equal to zero and provides a condition signal to indicate if the condition of the instruction was satisfied. If the condition of the instruction is satisfied, an offset value plus one is added to a program counter value. Otherwise, the program counter value is incremented by one.

System and method for executing branch on bit set/clear instructions

A data processor (10) increments a sixteen bit program counter value using an arithmetic logic unit, ALU, (224) and an eight bit incrementer(250). The ALU increments a low byte of the program counter value. A carry generated by incrementing the low byte is propagated to the incrementer. The incrementer then increments the high byte of the program counter value. Subsequently, the high and low bytes of the program counter value are respectively stored in a high and low program counter register (200, 206). Therefore, eight bits of an incrementer which would have typically been required to implement an incrementer for the low byte of the program counter value have been eliminated without a reduction in functionality of the data processor.

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Austin, TX, United States of America

James S Divine