Intel Corporation

James S Coke

Bret L Toll

Scott Dion Rodgers

Frank Binns

Peter J Ruscito

David B Jackson

Masood Tahir

Mohammad A Abdallah

Ves A Naydenov

Patrice L Roussel

Vladimir M Pentkovski

Gilbert A Neiger

Martin Guy Dixon

Baiju V Patel

Jason W Brandt

Shreekant S Thakkar

James B Crossland

Asit K Mallick

David D Lent

Dahmane Dahmani

Shay Gueron

Jesse R Walker

Jasmin Ajanovic

Ernie F Brickell

Srinivas Chennupaty

H Peter Anvin

Stephen Anthony Fischer

Howard C Herbert

William W Macy, Jr

Ajay V Bhatt

Eric L Debes

Nilesh V Shah

Xiaoning Li

David Johnston

Adriaan Van De Ven

George W Cox

Toby Opferman

Sathyamurthi Sadhasivan

Jeffrey L Rabe

Charles E Dike

Jonathan Jay Tyler

Ticky Thakkar

Micheal D Cranford

Atul A Khare

Edward V Gamsaragan

Katherine Kong

Stephen T Rowland

Rajeev K Prasad

Brian L Vajda

Gunendran Thuraisingham

Vladmir Pentkovski

Steve Fischer

Greg W Piper

Dave Smyth

Mitchell W Dale

Stan Graham

Mohammed A Abdallah

Vesselin Naydenov

Apparatuses and methods for supervisor mode execution protection are disclosed. In one embodiment, a processor includes an interface to access a memory, execution hardware, and control logic. A region in the memory is user memory. The execution hardware is to execute an instruction. The control logic is to prevent the execution hardware from executing the instruction when the instruction is stored in user memory and the processor is in supervisor mode.

Supervisor mode execution protection

An example processing system may comprise: a lower stack bound register configured to store a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register configured to store a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic configured to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address.

Systems and methods for preventing unauthorized stack pivoting

An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.

Dual function system and method for shuffling packed data elements

Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the privilege agnostic segment base register write instruction, wherein the privilege agnostic write instruction includes a 64-bit data source operand, decoding the fetched privilege agnostic segment base register write instruction, and executing the decoded privilege agnostic segment base register write instruction to write the 64-bit data of the source operand into the segment base register identified by the opcode of the privilege agnostic segment base register write instruction.

System, apparatus, and method for segment register read and write regardless of privilege level

A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

Length determination of instruction code with address form field and escape opcode value by evaluating portions other than instruction specific opcode

A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source 'extra' bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.

Digital random number generator using partially entropic data

Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode

Determining length of instruction with escape and addressing form bytes without evaluating opcode

Determining length of instruction with multiple byte escape code based on information from other than opcode byte

A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.

Executing partial-width packed data instructions

A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on data elements in said first packed byte data and said second packed byte data to generate a third packed data in response to receiving an instruction. A plurality of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data.

Method and apparatus for performing multiply-add operations on packed byte data

A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. The first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, the second set of instructions specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either of the first or the second set of instructions.

A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions

A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers. The partial-width execution unit is configured to execute operations specified by either of the first or the second set of instructions.

Growing community of inventors

Shingle Springs, CA, United States of America

James S Coke