Intel Corporation

James S Chung

Oleg Golonzka

Nadia M Rahhal-Orabi

Ajay K Sharma

Anthony A St Amour

Peter J DesRosier

Silvio Picano

Sridhar Jayaraman

An embodiment of the present invention is a technique to provide a parallel test mode for multi-core processors. A test access port (TAP) in a first processor core generates a first test data output (TDO) from a first test data input (TDI) or a first delayed TDI according to a TDO select bit. The first delayed TDI is clocked by a test clock (TCK). The first processor core has a first core circuit. The TAP generates a phase select word. A clock generator generates a clock signal synchronized with the TCK and has a low phase and a high phase. A first enable circuit enables first core data from the first core circuit in one of the low and high phases of the clock signal according to the phase select word.

Parallel test mode for multi-core processors

The performance of NMOS and PMOS regions of integrated circuits is improved. Embodiments of the invention include forming a first dielectric layer optimized for n-doped regions over the n-doped regions and forming a second dielectric layer optimized for p-doped regions over p-doped regions.

Enhanced nitride layers for metal oxide semiconductors

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Portland, OR, United States of America

James S Chung