Motorola Corporation

Aeroflex Utmc Microelectronic Systems, Inc.

James Rodney Webster

Clinton C Powell, Ii

James Michael Keba

Kevin T McLaughlin

Chun-Ye Susan Chang

Manbir Nag

Timothy Allan Melchior

Thaddeus Michael Firlit

A search coprocessor card for attachment to a computer system has an interface to a host processor of the computer system and a processor. The processor has memory for its program and data, and is coupled to one or more search engine devices. Each of the search engine devices is in turn coupled to a memory for holding key tables, and is capable of searching the key tables for matching entries.

Search coprocessor subsystem having multiple search engines and dedicated key-table memory for connection to a computer system

A digital demodulator ( ) includes a differentiate and cross multiply stage ( ) and a plurality of filter/decimator stages ( and and ) that accept both multiple baud rates and multiple modulation deviation frequencies, and that provide a common frequency data stream at their respective outputs. One of said filter/decimator stages is coupled to a primary filter ( ) which is followed by a box filter ( ). The box filter ( ) improves the overall filter response and provides notches at a specified frequency (e.g., 4800 Hz) and its harmonics. Demodulator ( ) provides improved sensitivity without the need for any circuit trimming. The filter stages (e.g., and ) used in demodulator ( ) have been optimized to eliminate the need for costly multipliers.

Digital demodulator using boxcar filters and boxcar filter sections

A method (900) and circuit (400) for automatic frequency correcting a frequency modulated (FM) digital signal determines a frequency offset value of the detected FM signal during a preamble portion of the FM digital signal, generates an offset corrected signal by removing the frequency offset value from a detected FM signal (440), and generates a frequency corrected signal (460). The frequency corrected signal is generated by selecting the offset corrected signal during the preamble portion, selecting the detected FM signal after the end of the preamble portion when a magnitude of the frequency offset value of the detected FM signal is below a predetermined threshold (445), and otherwise selecting the offset corrected signal after the end of the preamble portion.

Frequency shift modulation automatic frequency correction circuit and

A symbol synchronizer (10) for use in a communication device. The symbol synchronizer (10) comprises a sampling circuit (100) which samples the demodulated signal at a plurality of sampling events for each symbol period to generate three sample values at each sampling event. An eye pattern detector circuit (200) generates eye pattern characteristic information based on the three sample values, and outputs a symbol pulse in response to detecting eye pattern characteristic information consistent with a symbol center. A synchronization noise mask circuit (400) filters symbol pulses that occur during a predetermined period of time after a first symbol pulse is detected for each symbol period. A synchronization adjust circuit (500) generates a synchronization pulse during each symbol period at a particular instant of time during the symbol period based on a history of the occurrences of symbol pulses for a current symbol period and for prior symbol periods.

Symbol synchronizer based on eye pattern characteristics having variable

A selective call unit (800) comprising a receiver (100) and a processor (810) is used for decoding a 2-level radio signal. The processor (810) is adapted to convert in-phase and quadrature signals generated by the receiver (100) to a sequence of state transitions representative of the plurality of symbols. For each symbol in the plurality of symbols, the processor (810) counts the sequence of state transitions during a symbol period, and compares the recorded count to a predetermined threshold, thereby generating a comparison result. The processor (810) then calculates a bit decision threshold level based on an average of the comparison result for each symbol in the plurality of symbols. For each symbol in a plurality of subsequent symbols, the processor (810) then compares the bit decision threshold level to the sequence of state transitions counted during a symbol period to decode a digital logic level therefrom.

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Boynton Beach, FL, United States of America

James Rodney Webster