Hewlett-packard Development Company, L.p.

James Robert Peterson

Andrew Ray Wheeler

Darel N Emmot

Matthew B Lovell

This application relates to hardware based memory scrubbing. One disclosed embodiment may comprise a system that includes an engine, implemented in hardware, configured to initiate a request for data residing in associated memory. An error system is configured to detect errors in data that has been read from associated memory in response to the request for the data, the error system maintaining a log of entries corresponding to errors detected by the error system. An identifier is associated with each of the entries in the log that result from the request initiated by the engine to differentiate from other entries in the log.

Hardware based memory scrubbing

Systems and methods for configuring a computer system are disclosed. One embodiment of a system may comprise memory that stores configuration data for a plurality of components of a computer system. A configuration system operates to access the configuration data from the memory and to program at least one of the plurality of components based on corresponding configuration data from the memory while inhibiting operation of at least another portion of the computer system.

System and method for configuring a computer system

One disclosed embodiment may comprise a computer system that includes at least one processor having at least one cache. An interface includes an associated cache, the interface preloading the associated cache with instruction data acquired from non-volatile memory as part of a reset sequence so that the instruction data in the associated cache is available to the at least one cache of the at least one processor to facilitate reset by the computer system.

System and method to facilitate reset in a computer system

A method for allocating buffer capacity includes determining at least one characteristic of a first input/output (I/O) device that is coupled to a memory device interface, the memory device interface being configured to enable data transfers between the I/O device and a memory device, and buffering data corresponding to the first I/O device in a first portion of a buffer of the memory device interface, a size of the first portion being responsive to the at least one characteristic of the first I/O device.

Growing community of inventors

Fort Collins, CO, United States of America

James Robert Peterson