Cray Incorporated

James Robert Kohn

Steven Lee Scott

Gregory J Faanes

William T Moore, Jr

Sanyam Mehta

Luiz DeRose

Heidi Lynn Poxon

Daniel Jonathan Ernst

Brick Stephenson

Robert L Alverson

Michael A Parker

Eric P Lundberg

Andrew B Hastings

Abdulla Bataineh

Kitrick Sheets

Robert Baird

Josh Williams

Timothy J Johnson

James G Bravatto

Jonathan Gettler

Steve Piatz

Peter Hill

Vincent J Graziano

Greg Titus

A method for prefetching data into a cache is provided. The method allocates an outstanding request buffer ('ORB'). The method stores in an address field of the ORB an address and a number of blocks. The method issues prefetch requests for a degree number of blocks starting at the address. When a prefetch response is received for all the prefetch requests, the method adjusts the address of the next block to prefetch and adjusts the number of blocks remaining to be retrieved and then issues prefetch requests for a degree number of blocks starting at the adjusted address. The prefetching pauses when a maximum distance between the reads of the prefetched blocks and the last prefetched block is reached. When a read request for a prefetched block is received, the method resumes prefetching when a resume criterion is satisfied.

High-bandwidth prefetcher for high-bandwidth memory

A computerized method, apparatus, and executable instructions on a machine readable medium for using multiple processors in parallel to create a pack vector from an array in memory. In some embodiments creating the pack vector includes reading portions of the array into a plurality of processors that each select a subset of elements from the their respective portions of the array based on a predetermined criteria. Some embodiments further include counting each of the selected subsets of elements and storing each count in a commonly accessible storage location, reading into the processors at least some of the count values once all of the processors have stored their count, and storing only the selected subsets of elements in the pack vector based at least in part on the count values.

Multistreamed processor vector packing method and apparatus

A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.

Configurable vector length computer processor

A method and apparatus to provide specifiable ordering between and among vector and scalar operations within a single streaming processor (SSP) via a local synchronization (Lsync) instruction that operates within a relaxed memory consistency model. Various aspects of that relaxed memory consistency model are described. Further, a combined memory synchronization and barrier synchronization (Msync) for a multistreaming processor (MSP) system is described. Also, a global synchronization (Gsync) instruction provides synchronization even outside a single MSP system is described. Advantageously, the pipeline or queue of pending memory requests does not need to be drained before the synchronization operation, nor is it required to refrain from determining addresses for and inserting subsequent memory accesses into the pipeline.

Relaxed memory consistency model

A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, one vector register is loaded with the 'add-in' values, and another vector register is loaded with address values of 'add to' elements to be gathered from memory into a third vector register. If the vector of address values has a plurality of elements that point to the same memory address, the algorithm should add all the &#x201c;add in&#x201d; values from elements corresponding to the elements having the duplicated addresses. An indirectly addressed load performs the &#x201c;gather&#x201d; operation to load the &#x201c;add to&#x201d; values. A vector add operation then adds corresponding elements from the &#x201c;add in&#x201d; vector to the &#x201c;add to&#x201d; vector. An indirectly addressed store then performs the &#x201c;scatter&#x201d; operation to store the results.

Method and apparatus for indirectly addressed vector load-add-store across multi-processors

Systems and methods for scheduling program units that are part of a process executed within an operating system are disclosed. Additionally, at least one thread is started within the operating system, the thread is associated with the process. Further, a plurality of streams within the thread are selected for execution on a multiple processor unit. Upon the occurrence of a context shifting event, one of the streams enters a kernel mode. If the first stream to enter kernel mode must block, then the execution of the other streams of the plurality of streams is also blocked.

Scheduling synchronization of programs running as streams on multiple processors

Multistream processing memory-and barrier-synchronization method and apparatus

Method and apparatus for indirectly addressed vector load-add -store across multi-processors

Indirectly addressed vector load-operate-store method and apparatus

A method and system for selectively enabling a cache-invalidate function supplement to a resource-synchronization instruction such as test-and-set. Some embodiments include a first processor, a first memory, at least a first cache between the first processor and the first memory, wherein the first cache caches data accessed by the first processor from the first memory, wherein the first processor executes: a resource-synchronization instruction, an instruction that enables a cache-invalidate function to be performed upon execution of the resource-synchronization instruction, and an instruction that disables the cache-invalidate function from being performed upon execution of the resource-synchronization instruction.

Instructions for test & set with selectively enabled cache invalidate

Growing community of inventors

Inver Grove Heights, MN, United States of America

James Robert Kohn