Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Intel Corporation

Marvell International Limited

James Robert Feddeler

Michael Todd Berens

Stefano Pietri

Zahid Ahsanullah

Miten H Nagda

Yizhong Zhang

Michael A Stockinger

Kenneth R Burch

Ricardo Pureza Coimbra

Alfredo Olmos

Michael L Longwell

Dale John McQuirk

Vasudev Bibikar

Michael C Wood

Sanjoy Kumar Dey

Robert Matthew Mertens

Vikram Varma

Gregory A Racino

Gregory V Rose

Juan Camilo Monsalve

Mark N Fullterton

Xiang Yang Li

Mohit Arora

Nathan Y Moyal

Carl Culshaw

Ammisetti Prasad

Khoi Mai

Derek Beattie

Alan Devine

Martin Mienkina

Prashant Bhargava

James Andrew Collier Scobie

Simon Gallimore

George E Baker

Daniel Mark Thompson

Michael Ren Kent

Linda R Nuckolls

Nidhi Chaudhry

Gregory C Edgington

Vincent B Deems

Raha K Prasun

Greg A Racino

Edward M Stellini

Timothy E Barnard

William Edward Getka

Richard W Moseley

Victor E Shiff

Mihir Suchak

A clock generation circuit includes a switched capacitor circuit for providing a discrete amount of charge to a resonator for sustaining energization of the resonator at specific portions of the clock cycle.

Clock generation

An electronic switch that includes a signal path with a first terminal side of the signal path including cascoded transistors in the signal path. When the switch is in an off state, the gate of one of the cascoded transistors is biased at an intermediate voltage different from the voltage applied to the gate of the other of the cascoded transistors. In one embodiment, having the gate of one of the cascoded transistors biased at an intermediate voltage in an off state may reduce leakage current into a signal terminal of the switch. The electronic switch includes an injection shunting device (e.g. such as a transistor) connected to a node of the signal path. In one embodiment, the injection shunting device prevents the voltage of the node from reaching a specific voltage level due to leakage current when the switch is in an off state.

Electronic switch

A low power crystal oscillator is provided. The crystal oscillator includes a gain control stage, a filter stage, and an output stage. The gain control stage includes an input coupled at a first oscillator terminal configured and arranged for connection to a first terminal of a crystal. The filter stage includes an input coupled to an output of the gain control stage. The output stage includes a first transistor having a first current electrode coupled at a second oscillator terminal configured and arranged for connection to a second terminal of the crystal and a control electrode coupled to receive a voltage signal at the first oscillator terminal and a first bias voltage.

Low power crystal oscillator

A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.

Segmented resistive digital to analog converter

A digital to analog converter receives a digital input consisting of first least significant bits, second most significant bits, and third middle significant bits. The digital to analog converter includes first, second, and third sub-DACs. The first sub-DAC receives the first least significant bits, and includes first resistors each contributing a respective voltage, to provide a first output. The second sub-DAC receives the second most significant bits, and includes second resistors each contributing a respective voltage, to provide a second output as an output of the digital to analog converter. The third sub-DAC is connected to the first sub-DAC to receive the first output, and receives the third middle significant bits, and includes third resistors each contributing a respective voltage, to provide a third output to the second sub-DAC. The first and third resistors each has a physical area less than an area of each second resistor.

Segmented digital to analog converter

A method of powering up a circuit includes powering up a latch circuit in a known latch state by applying a first power supply voltage differential of a first voltage domain across power supply terminals of the latch circuit. A current diode inhibits current diode in a current path between a latch node of the latch circuit and a power supply terminal when the power supply voltage differential is below a threshold voltage during the powering up in which the inhibiting prevents the latch circuit from switching from the known latch state during the powering up.

Power on reset latch circuit

A first voltage scaling power switch is coupled to a first power supply terminal for providing power to a first circuit portion, and a second voltage scaling power switch is coupled between the first power supply terminal providing power to a second circuit portion. A common power rail is coupled the first and second power input nodes during respective voltage scaling modes of the first and second circuit portions. A feedback circuit coupled to the common power rail provides a feedback signal to a control input of the first voltage scaling power switch to regulate a voltage provided by the first power switch, and to a control input of the second voltage scaling power switch to regulate a voltage provided by the second voltage scaling power switch.

Circuit with multiple voltage scaling power switches

An analog-to-digital converter (ADC) includes a split-capacitor digital-to-analog converter (DAC) having a Most Significant Bits (MSBs) sub-DAC with one or more MSBs encoded with one or more binary capacitors and one or more MSBs encoded with one or more thermometer capacitors, a Least Significant Bits (LSBs) sub-DAC, a termination capacitor coupled to the LSBs sub-DAC, and a scaling capacitor coupled between the LSBs and MSBs sub-DACs, and coupled to receive an analog input voltage, a high reference voltage, and a low reference voltage, and to provide an output voltage. The ADC includes a comparator coupled to receive the output voltage, successive-approximation-register (SAR) circuitry coupled to the comparator and providing an uncalibrated digital value corresponding to an uncalibrated digital representation of the input voltage, and calibration circuitry configured to apply one or more calibration values to the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital.

Analog-to-digital converter (ADC) having calibration

An integrated circuit includes an I/O pad and a protection device coupled to the I/O pad and a first supply node. A transient event detector includes a latch; a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to a first supply node, and a second current electrode coupled to a data input of the latch, wherein the latch is configured to store an indication that a transient event occurred. An event level sensor includes a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to the protection device, and a second current electrode coupled to a load circuit; a rectifier device coupled between the second current electrode and a capacitor; a second transistor having a control electrode coupled to the capacitor; and an output circuit configured to place a current on a first sense bus proportional to a current through the load circuit.

Sensing and detection of ESD and other transient overstress events

A digital to analog converter (DAC) includes a first sub-DAC configured to convert most significant bits (MSBs) of digital input data, the first sub-DAC including a first array of resistors, a second sub-DAC configured to convert at least some least significant bits (LSBs) of the digital input data, the second sub-DAC including a second array of resistors, and a first scaling resistor connected between the first and second sub-DACs, wherein the first scaling resistor has a resistance value that is based on the number of resistors in the second sub-DAC.

Digital to analog converter (DAC) having sub-DACs with arrays of resistors

A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.

Method and apparatus for limiting access to an integrated circuit (IC)

Systems and methods for electronically converting an analog signal to a digital signal are disclosed. The systems and methods may include, for a first bit value, setting a first conversion value to include a first offset; using the output of a first comparison, setting a second conversion value; and if the first bit value has a predetermined relationship to the first offset bit value, removing the first offset from the second conversion value, and, using the output of a second comparison, setting a third conversion value.

Systems and methods for data conversion

A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Method and apparatus for self-test of successive approximation register (SAR) A/D converter

A system for compensating for variations in the frequency of an input clock signal having a first frequency includes a coarse counter that receives the input clock signal, counts a predetermined number of clock pulses of the input clock signal, and generates a coarse compensated clock signal having a second frequency. A first compensation module adjusts a clock pulse of the input clock signal based on a coarse compensation value. A residual period adjustment module accumulates a fine compensation value for each clock pulse of the coarse compensated clock signal. A fine counter operates at a third frequency of a fine clock signal, receives an adjusted delay value based on the accumulated fine compensation value, counts a number of fine clock pulses in each clock pulse of the coarse compensated clock signal, and generates a fine compensated clock signal having the second frequency.

System for compensating for variations in clock signal frequency

Growing community of inventors

Austin, TX, United States of America

James Robert Feddeler