Ami Semiconductor, Inc.

Westinghouse Electric Corporation

James Robert Brown

Brian R Kauffmann

Charles A Edmondson

Robert S Kirk

Shan Mo

Rick A Olson

Richard A Mosher

A dynamic phase adjustment circuit that includes a multi-tap delay line that receives a clock input signal. The multi-tap delay line includes an initial portion that is adjustable, and final portion after the adjustable portion. A number of registers receive the same data. However, the clock signal that causes the registers to sample is received from a corresponding delay element in the final portion of the multi-tap delay line. An edge detect and data decision circuit receives the sampled data values from each of the registers. Sampling resolution is improved over the PLL-based dynamic phase adjustment circuit since the clock signal is delayed using delay elements, which can be made with relatively small delays. Furthermore, the circuit does not contain excessive circuit elements thereby allowing the dynamic phase adjustment circuit to be contained in a small area.

Dynamic phase alignment of a clock and data signal using an adjustable clock delay line

Systems and methods are disclosed for distributing memory within one or more regions of circuitry that perform logic functions (or other types of functions that require dense interconnect structures) on an integrated circuit. The distributed memory reduces high density routing congestion, allows increased logic utilization, and provides areas for additional interconnect structure. Various techniques are also disclosed for accessing the memory.

Distributed memory and logic circuits

An SRAM memory includes a pull-up device coupled to each row of word lines in an array of SRAM cells. The pull-up devices are sized such that when a row is selected, the time for the associated word line to fully charge is sufficiently slow such that data stored in the selected SRAM cells are not corrupted during a read operation. By slowly charging the word lines, the corresponding access transistors are also slowly turned on, resulting in the coupled bit lines slowly charging or discharging from the data stored in the SRAM cell. Because there is not a sudden large charge transfer between the stored data and the coupled bit line, the data will not be corrupted during a read operation, and read precharge circuitry is not required.

Static random access memory (SRAM) without precharge circuitry

A memory initialization circuit includes one or more duplicated pairs of bit lines, which may be used to initialize the memory cells of a memory array to different logical values. When an initialization signal is asserted on the initialization circuit, the individual bit lines in the pair of bit lines are set to opposite logical values, for instance setting one bit line to a logical zero and the other to a logical one. This occurs without regard to external data values received by the circuit. When the initialization signal is removed, individual bit lines in a duplicated pair carry identical values, which may be equal to external data values that are received by the circuit. Thus, after initialization, memory cells function as if duplicated pairs were not included in the circuit. A memory array may be initialized to a predetermined pattern by coupling different combinations of memory cells to different bit lines from duplicated pairs.

Circuits and methods for initializing memory cells

A roller structure for a rotary machine has a plate that is removably engagable with the outer casing of such rotary machines, a shaft portion attached to the plate and insertable through the outer casing, a bearing mounted for rotation upon the shaft portion, and a selected plurality of shims having different thicknesses engagable upon the shaft portion to adjust the position of the bearing with respect to an inner casing of the rotary machine.

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Idaho Falls, ID, United States of America

James Robert Brown