Unisys Corporation

Jst Performance, LLC

James Rhodes

Robert David Conklin

Terry Sinclair Connacher

Timothy Allen Barr

James Mason Brafford

David Jon Mortensen

Randy Neaman Siade

John Charles Montgomery

Stephen P Adams

Robert H Carlson

Carl L Ostrowski

An LED lamp is placed in service on an automotive vehicle to enhance nighttime visual ability or anywhere where increased lighting is needed. The LED lamp utilizes a multi-stage power and control design, where the LED drive current is managed by an LED constant current controller that is coupled to a microprocessor that commands the intensity value of an LED array. The microprocessor manages the light intensity of the LED array using well known pulse-width modulation control methods. The microprocessor measures the voltage of the DC power source and to detect when DC power is removed. Once this detection has occurred, the microprocessor signals the LED current controller to change the current operational mode being delivered to the LED array to the next available operational mode, or alternatively, to the next appropriate operational mode to be used as determined by software stored within the microprocessor.

LED device with power removal detection and method for using the same

An electromechanical module, for holding IC-chips in a chip testing system, includes a circuit board having a plurality of sockets mounted thereon. Each socket is structured to hold one IC-chip that is to be tested, and each socket has a corresponding register on the circuit board. In addition, a bus is on the circuit board, which&#x2014;a) sends a timing pulse to a clock input on all of the registers in parallel, and b) concurrently sends a clock signal and N&#x2212;1 test signals to N data inputs on all of the registers. Further, each socket has N input terminals that are connected to N outputs on a respective set of signal translators on the circuit board, and each set of signal translators has N inputs that are connected to N data outputs on the socket's corresponding register.

Electromechanical module, for holding IC-chips in a chip testing system, that synchronizes and translates test signals to the IC-chips

An electromechanical system for testing IC-chips includes a total of N chip holding subassemblies, where N is an integer greater than one and where each chip holding subassembly has sockets for holding a group of IC-modules that include the IC-chips; a moving mechanism for automatically moving the i-th chip holding subassembly from a load position in the system to a test position in the system, and visa-versa, where i ranges from 1 to N and changes with time in a sequence; and a temperature control mechanism which contacts the IC-modules at the test position. Between the moving of the i-th chip holding subassembly and the next chip holding subassembly in the sequence, the IC-chips are burn-in tested on all N of the chip holding subassemblies. Also, while the i-th chip holding subassembly is being moved, burn-in testing of IC-chips on the remaining N-1 chip holding subassemblies continues.

System for testing one or more groups of IC-chips while concurrently loading/unloading another group

An electromechanical system for testing IC-chips includes a chip holding subassembly which has sockets for holding a group of IC-modules that include the IC-chips; a moving mechanism for automatically moving the chip holding subassembly from a load position in the system to a test position in the system, and visa-versa; a temperature control mechanism which contacts the IC-modules on the chip holding subassembly only when that subassembly is at the test position; and a chip handler mechanism for automatically moving the IC-modules into and out of the sockets, when the chip holding subassembly is at the load position. At the test position, the temperature control mechanism contacts the IC-modules to control their temperature. At the load position, the chip handler mechanism automatically unloads one group of IC-modules from the sockets on the chip holding subassembly and automatically loads another group of the IC-modules into the sockets.

System for testing a group of IC-chips having a chip holding subassembly that is built-in and loaded/unloaded automatically

An electromechanical system for testing IC-chips includes a total of N chip holding subassemblies; a moving mechanism for automatically moving the i-th chip holding subassembly from a load position in the system to the test position in the systems, and visa-versa, where i ranges from 1 to N and changes with time in a sequence; and a signal generator which sends test signals to the IC-chips at the test position. Between the moving of the i-th chip holding subassembly and the next subassembly in the sequence, test signals are sent to the IC-chips on all N of the chip holding subassemblies such that the signals are shifted in time from one subassembly to another. Also, while the i-th chip holding subassembly is being moved, the time shifted test signals continue to be sent to the IC-chips on the remaining N&#x2212;1 chip holding subassemblies.

System for testing multiple groups of IC-chips which concurrently sends time-shifted test signals to the groups

An initial stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of multiple sets of input registers which store respective addresses; and an address modifying circuit that is coupled to the input registers, which receives commands, and in response, selects one register in one set and generates a modified address by performing arithmetic operations on the address in the selected register. Also, the initial stage includes a boundary check circuit that is coupled to the address modifying circuit, which stores a respective minimum limit and a respective maximum limit for each register set. This initial stage is particularly useful in generating sequences of addresses for memory cells in a chip that is to be tested, where the cells are arranged in rows and columns. When a particular Min/Max limit for a row/column is reached, then that event is remembered by the boundary check circuit. Thereafter, when the next row/column address is generated, the boundary check circuit automatically replaces the generated address (which will exceed the limit) with the proper address. This operation of detecting a limit address in one cycle, and replacing the next generated address in a subsequent cycle, enables the cycle time of the initial stage to be shorter than it otherwise could be if detection outside the limit and replacement with the proper address, occur in a single cycle.

Initial stage of a multi-stage algorithmic pattern generator for testing IC chips

An output stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of multiple input registers which hold input addresses and input data words; and a multiplexer circuit, having a plurality of parallel data inputs which concurrently receive the input addresses and the input data words, having control inputs for receiving a sequence of control signals, and which generates serial bit streams by selectively passing bits from the input addresses and input data words in response to the control signals. These serial bit streams from the multiplexer circuit preferably include a first bit stream which defines a data input to an integrated circuit chip that is to be tested, and a second bit stream which defines an expected output from the chip corresponding to the first bit stream. In one particular embodiment, the output stage further includes a memory address generator which generates a sequence of memory addresses, and a memory which receives the sequence of memory addresses, and in response, sends the sequence of control signals from a memory output to the control inputs of the multiplexer circuit. With this embodiment, the memory address generator can include a page register and a counter which together generate the sequence of memory addresses as multiple sub-sequences within respective pages; and the sub-sequences can be generated continuously with no gaps between them so that the serial bit streams from the multiplexer circuit will be generated continuously with no gaps between the serial bits.

Output stage of a multi-stage algorithmic pattern generator for testing IC chips

An intermediate stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of a plurality of input address registers which hold respective input addresses; and a memory address generator, coupled to the input address registers, which generates a series of memory addresses by selecting bits from the input addresses. A memory is coupled to the memory address generator, which sequentially receives each memory address in the series; and in response, this memory sends a corresponding series of translated addresses to a memory output. Multiple output registers are coupled to the memory output, and each output register stores a respective translated address in the series. With this intermediate stage, the input addresses can be virtual addresses in a virtual, or hypothetical, memory; and, those virtual addresses can be translated into physical addresses for an actual memory chip that is to be tested.

Intermediate stage of a multi-stage algorithmic pattern generator for testing IC chips

A multi-stage algorithmic pattern generator, which generates bit streams for testing IC chips, is comprised of an initial stage, an intermediate stage, and an output stage which are coupled together as a three stage pipeline. The initial stage sequentially generates multiple sets of virtual addresses for a virtual memory in response to a series of instructions from an external source. The intermediate stage sequentially stores each set of virtual addresses from the initial stage and translates the stored set of virtual addresses into a set of physical addresses for an actual memory that is to be tested. The output stage sequentially stores each set of physical addresses from the intermediate stage and generates output signals for testing the memory chips, by selecting bits from the stored set of physical addresses.

Multi-stage algorithmic pattern generator for testing IC chips

A system for testing IC chips selectively with stored or internally generated bit streams is comprised of a memory which stores instructions of a first class that expressly recite a first bit stream, and stores instructions of a second class that specify operations which generate a second bit stream. A first pattern generator is coupled to the memory, which sequentially reads the instructions of the first and second classes. The first pattern generator includes a time-shared control circuit which sends the first bit stream to a test port on the chips that are tested in response to the first class instructions that are read. In addition, a second pattern generator is coupled to the first pattern generator. This second pattern generator receives the second class instructions that are read; and in response, it sequentially generates portions of the second bit stream by performing the operations which the second class instructions specify. One portion of the second bit stream is sent to the test port on the chips that are tested, while the second pattern generator generates another portion of the second bit stream.

System for testing IC chips selectively with stored or internally generated bit streams

A system for testing integrated circuit chips is comprised of a pattern generator that is coupled to a memory which stores variable length instructions that specify sets of bit streams for testing the chips. Each variable length instruction includes a code which indicates the number of bit streams in the set. Each bit stream in the set consists of a selectable number of bits which start on a word boundary and vary in increments of one bit. If the code indicates that the number of bit streams in a set is only one, then that one bit stream is stored in consecutive words of the memory. If the code indicates the number bit streams in a set is more than one, then those multiple bit streams are stored in an interleaved fashion in consecutive words in the memory. A respective series of unused bits starts immediately after each bit stream and ends on a word boundary. Each series of unused bits causes the next bit stream to start on a word boundary; and, that simplifies the circuitry which the pattern generator uses to address the bit streams.

Program storage device containing instructions that are spaced apart by unused bits that end on word boundaries and which generate chip testing bit streams of any length

A system for testing integrated circuit chips includes a signal generator which generates a clock signal; and a sequential control circuit having a first input which receives the clock signal, a second input for receiving commands, and multiple outputs. A command source sends programmable sequences of the commands to the second input of the control circuit; and in response, the control circuit passes the clock signal from the first input to only certain outputs which the commands select. All of the outputs of the control circuit are coupled through respective clock transmitters to different chips which are to be tested; and so in response to the programmable commands, the clock signal is sent sequentially to the chips that are to be tested, in selectable subsets. By such sequencing, the total power dissipation of the chips that are tested can be regulated when the chips are of a type that dissipate a large amount of power when they receive the clock signal, but dissipate substantially less power when they do not receive the clock signal.

Electronic system for testing a set of multiple chips concurrently or sequentially in selectable subsets under program control to limit chip power dissipation

A system for testing integrated circuit chips is comprised of a selectable number of pattern generators, each of which is coupled via a separate bus to a selectable number of chip driver circuits. Each pattern generator also is coupled to a respective memory, which stores different bit streams that are readable one word at a time. In operation, each pattern generator selectively reads the bit streams, word by word, from its respective memory; and its sends the words that are read to all of the chip driver circuits which are coupled to its separate bus, simultaneously. While that is occurring, each chip driver converts the words which it is sent into bit serial test signals which test multiple integrated circuit chips in parallel. Since all of the pattern generators operate in parallel, and since each pattern generator sends bit streams to all of the chip driver circuits that are coupled to its bus simultaneously, a high speed of operation is attained.

Electronic system for testing chips having a selectable number of pattern generators that concurrently broadcast different bit streams to selectable sets of chip driver circuits

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Chandler, AZ, United States of America

James Rhodes