Lsi Logic Corporation

James R Welch

Alan S Fiedler

Iain Ross Mactaggart

Iain R MacTaggart

A high speed capture latch includes differential data inputs, a latch clock input, a boost clock input, a current steering circuit, a switched current source, a latch element and first and second boost current sources. The current steering circuit has first and second differential control terminals which are coupled to the differential data inputs and control current through first and second current paths, respectively. The switched current source is coupled between the current steering circuit and a first voltage supply terminal and has a control terminal coupled to the latch clock input. The latch element is coupled between a second voltage supply terminal and the current steering circuit and provides a latch output. The first boost current source is coupled to the first current path between the latch element and the current steering circuit and has a control terminal coupled to the boost clock input. The second boost current source is coupled to the second current path between the latch element and the current steering circuit and has a control terminal coupled to the boost clock input.

High speed capture latch

A self-timed phase detector for detecting the phase of an input signal, such as a high speed serial data stream. The self-timed phase detector includes a precharged latch, a phase detector circuit and a data valid gate. The precharged latch has a latch input, a sample clock input and first and second complementary latch outputs. The first and second complementary latch outputs have an active state and a precharged state. The phase detector circuit is coupled to the first latch output and generates a phase signal on a phase output as a function of the phase of the input signal. The data valid gate is coupled to the phase output for passing the phase signal when the latch outputs are in the active state and for blocking the phase signal when the latch outputs are in the precharged state.

Self-timed phase detector and method

A phase locked loop locks on to the phase of a high speed serial data stream. The phase locked loop includes a multiple bit latch, a multiple-stage voltage controlled oscillator, a phase detection circuit and a feedback circuit. The multiple-bit latch has a plurality of data latch elements and boundary-detect latch elements. Each latch element includes a latch input for receiving the serial data stream, a sample clock input and a latch output. The multiple-stage voltage controlled oscillator has a voltage control input, a plurality of sample clock outputs and an adjustable delay between each sample clock output. Each sample clock output is coupled to a corresponding sample clock input. The phase detection circuit is coupled to the latch outputs of the data and boundary-detect latch elements and has a phase control output. A feedback circuit is coupled between the phase control output and the voltage control input.

Growing community of inventors

Maple Grove, MN, United States of America

James R Welch