International Business Machines Corporation

James R Urquhart

William John Starke

Eric M Schwarz

Casper A Scalzi

Douglas W Westcott

Charles E Shapley

Ravi Ranjan

Friedrich Beichter

John J Hughes

Brian K Zerba

David R Willoughby

Steven T Comfort

Arthur J Sutton

Bruce L McGilvray

Neal T Christensen

Robert J Hurban

Configuring of a communications environment is facilitated. A mapping tool is provided that aids in the configuring of various components of a communications environment, such as an input/output (I/O) subsystem of the environment. Data generated from an order process and a logical configuration definition are used as input to the mapping tool. The tool performs mapping and generates as output a physical configuration definition, and optionally, one or more reports. The mapping tool has a manual function, as well as an automatic function.

Mapping tool for configuring communications environments

Facilitating the configuring of communications environments

Preprocessing emulation methods utilizing search argument controls for a template routine address table in a target computing system. Target routines are stored in a target computing system for emulating incompatible instructions of an incompatible architecture which need not be recognized by the architecture of the target computing system. Preprocessing of template routines is preferrably executed on an Auxiliary Emulation Processor (AEP) which may access and patch (modify) some or all of the target instructions in any selected target routine and send them through a queue to a target processor for execution. Execution of the target routines on a target processor emulates the execution of incompatible instructions in an incompatible program in the incompatible architecture. The target processor feeds back results from the execution of target routines to modify any search argument being generated for a currently accessed incompatible instruction to allow the preprocessing selection among multiple target routines for any incompatible instruction currently executing on the target processor to represent any mode or state set by for the incompatible instruction. Another type of feed back from a currently executing target template routine enables non-sequential virtual addressing selection by the preprocessor's access of incompatible instructions during execution of the incompatible program to support incompatible instruction branches and incompatible authority controls. End routine controls are provided in the template routines for feedback synchronization of the accessing of each next incompatible instruction with execution results of each current incompatible instruction having its tempate routine currently executed by the target processor.

Preprocessing of stored target routines for controlling emulation of

Provides a program translation and execution method which stores target routines (for execution by a target processor) corresponding to incompatible instructions, interruptions and authorizations of an incompatible program written for execution on another computer system built to a computer architecture incompatible with the architecture of the target processor's computer system. The disclosed process allows the target processor to emulate incompatible acts expected in the operation of an incompatible program when the target processor itself is incapable of performing the emulated acts. Each of the instructions, interruptions and authorizations found in the incompatible programs has one or more corresponding target routines, any of which may need to be preprocessed before it can precisely emulate the execution results required by the incompatible architecture. Target routines (corresponding to the incompatible instruction instances in an incompatible program being emulated) are accessed, patched where necessary, and executed by a target processor to enable the target processor to precisely obtain the execution results of the emulated incompatible program. Before preprocessing, each target routine may not be able to provide identical execution results as required by the incompatible architecture, and the preprocessing may patch one or more of its target instructions to enable the target routine to perform the identical emulation execution of the corresponding incompatible instruction. The patching and other modifications to a target routine are done by one or more preprocessing instructions stored in the target routine.

Preprocessing of stored target routines for emulating incompatible

A method of handling errors in the C bit of a storage key by modifying the INSERT STORAGE KEY (ISK) and the RESET REFERENCE BIT (RRB) instructions. If an error is found in the C bit during the execution of these instructions, microcode is instructed to refresh the C bit. The C bit is interrogated a second time to determine if the refreshed C bit is still in error. If the refreshed C bit is not in error a second time, then the first error was caused by a soft or transient error, and the instruction is continued. If the refreshed C bit is in error a second time then the first and second errors were caused by a permanent error such as a stuck bit, and a system recovery machine check error is generated. The handling of C bit errors is thus done in a dynamic fashion as the instructions are executed.

Handling errors in the C bit of a storage key

Growing community of inventors

Fishkill, NY, United States of America

James R Urquhart