Cornell Research Foundation Inc.

Cornell University

Power Integrations, Inc.

Odyssey Semiconductor, Inc.

Welch Allyn, Inc.

Northeast Semiconductor Inc.

James R Shealy

Richard J Brown

Joseph A Smart

Lester F Eastman

Yu-Hwa Lo

James R Engstrom

Alfred T Schremer

David P Bour

A Low Pressure Chemical Vapor Deposition (LPCVD) technique is provided to produce improved dielectric/semiconductor interfaces for GaN-based electronic devices. Using the LPCVD technique, superior interfaces are achieved through the use of elevated deposition temperatures (>700° C.), the use of ammonia to stabilize and clean the GaN surface, and chlorine-containing precursors where reactions with chlorine remove unwanted impurities from the dielectric film and its interface with GaN. The LPCVD silicon nitride films have less hydrogen contamination, higher density, lower buffered-HF etch rates, and lower pin hole density than films produced by other deposition techniques making the LPCVD coatings suitable for device passivation. A metal insulator semiconductor (MIS) structures fabricated with LPCVD SiN on GaN exhibit near ideal capacitance-voltage behavior with both charge accumulation, depletion, and inversion regimes.

Vertical gallium nitride containing field effect transistor with silicon nitride passivation and gate dielectric regions

In an example, the present invention provides a method of forming a semiconductor device on a gallium and nitrogen containing material. The method includes providing a substrate member comprising a surface region, the substrate member comprising a gallium and nitrogen bearing material. The method includes causing an implanted species to electrically activate the implant profile while removing one or more crystalline damage from the epitaxial material to change the amorphous state to a single crystalline state, and thereby creating a substantially electrically activated crystalline material.

Method for implant and anneal for high voltage field effect transistors

The invention described herein provides a method and apparatus to realize incorporation of Beryllium followed by activation to realize p-type materials of lower resistivity than is possible with Magnesium. Lower contact resistances and more effective electron confinement results from the higher hole concentrations made possible with this invention. The result is a higher efficiency GaN-based LED with higher current handling capability resulting in a brighter device of the same area.

Beryllium doped GaN-based light emitting diode and method

A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n− type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

Vertical field effect transistor device and method of fabrication

A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n&#x2212; type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n&#x2212; type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

A method for fabricating a semiconductor structure includes forming a semiconductor layer over a substrate and forming an aluminum-silicon nitride layer upon the semiconductor layer. When the semiconductor layer in particular comprises a III-V semiconductor material such as a group III nitride semiconductor material or a gallium nitride semiconductor material, the aluminum-silicon nitride material provides a superior passivation in comparison with a silicon nitride material.

Method for forming III-V semiconductor structures including aluminum-silicon nitride passivation

A semiconductor structure includes a semiconductor layer that is passivated with an aluminum-silicon nitride layer. When the semiconductor layer in particular comprises a III-V semiconductor material such as a group III nitride semiconductor material or a gallium nitride semiconductor material, the aluminum-silicon nitride material provides a superior passivation in comparison with a silicon nitride material.

III-V semiconductor structures including aluminum-silicon nitride passivation

A gated III-V semiconductor structure and a method for fabricating the gated III-V semiconductor structure includes a threshold modifying dopant region within a III-V semiconductor barrier layer at the base of an aperture through a passivation layer that otherwise passivates the III-V semiconductor barrier layer. The passivation layer, which may comprise an aluminum-silicon nitride material, has particular bandgap and permittivity properties that provide for enhanced performance of a III-V semiconductor device that derives from the III-V semiconductor structure absent a field plate. The threshold modifying dopant region provides the possibility for forming both an enhancement mode gated III-V semiconductor structure and a depletion mode III-V semiconductor structure on the same substrate. The threshold modifying dopant region when comprising a magnesium (Mg) threshold modifying dopant may be incorporated into the gates III-V semiconductor structure using a dicyclopentadienyl magnesium (Cp2Mg) vapor diffusion method or a magnesium-silicon nitride (MgSiN) solid state diffusion method.

Gated III-V semiconductor structure and method

A chemical vapor deposition method for forming an aluminum-silicon nitride layer upon a substrate uses an aluminum precursor, a silicon precursor and a nitrogen precursor under chemical vapor deposition conditions to deposit the aluminum-silicon nitride layer upon the substrate. The aluminum-silicon nitride layer has an index of refraction interposed between silicon nitride and aluminum nitride. The aluminum-silicon nitride layer also has a bandgap from about 4.5 to about 6 eV and a permittivity from about 6&#xd7;10^-11 to about 8&#xd7;10^-11 F/m. The aluminum-silicon nitride layer may be further thermally annealed to reduce a hydrogen content of the aluminum-silicon nitride layer.

Chemical vapor deposition process for aluminum silicon nitride

A single step process for nucleation and subsequent epitaxial growth on a lattice mismatched substrate is achieved by pre-treating the substrate surface with at least one group III reactant or at least one group II reactant prior to the introduction of a group V reactant or a group VI reactant. The group III reactant or the group II reactant is introduced into a growth chamber at an elevated growth temperature to wet a substrate surface prior to any actual crystal growth. Once the pre-treatment of the surface is complete, a group V reactant or a group VI reactant is introduced to the growth chamber to commence the deposition of a nucleation layer. A buffer layer is then grown on the nucleation layer providing a surface upon which the epitaxial layer is grown preferably without changing the temperature within the chamber.

Single step, high temperature nucleation process for a lattice mismatched substrate

An epitaxial deposition process produces epitaxial lateral overgrowth (ELO) of nitride based materials directly a patterned substrate ( ). The substrate ( ) is preferably formed from SiC or sapphire, and is patterned with a mask ( ), preferably formed of silicon nitride, having a plurality of openings ( ) formed therein. A nucleation layer ( ), preferably formed of AlGaN, is grown at a high reactor temperature of 700-1100 degrees C., which wets the exposed substrate surface, without significant nucleation on the mask ( ). This eliminates the need for regrowth while producing smooth growth surfaces in the window openings ( ) as well as over the mask ( ). Subsequent deposition of a nitride based material layer ( ), preferably GaN, results in a relatively defect free planar surfaced material grown laterally over the mask ( ).

Single step process for epitaxial lateral overgrowth of nitride based materials

A field effect semiconductor device including a substrate, a dipole barrier formed on the substrate, a channel layer formed on the dipole barrier, and source, gate and drain electrodes formed on the channel layer. The dipole barrier provides a potential barrier and a maximum electric field sufficient to confine electrons to the channel layer.

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Ithaca, NY, United States of America

James R Shealy