International Business Machines Corporation

James R Salimeno, Iii

Timothy Dooling Sullivan

David Lewis Gardell

David Michael Audette

Dustin M Fregeau

Joseph K V Comeau

Frederick H Roy, Iii

Dennis M Bronson, Jr

Steven J Holmes

Louis C Hsu

Cherie Renee Kagan

David P Vallett

Leendert M Huisman

Hsichang Liu

Leah M Pastel

Paul William Pastel

Jerome L Cann

A probe tip structure that decreases the accumulation rate of Sn particles to the probe tip and enables considerably more efficient and complete laser cleaning is disclosed. In an embodiment, the probe structure includes an array of probe tips, each probe tip having an inner core; an interfacial layer bonded to the inner core; and an outer layer bonded to the interfacial layer, wherein the outer layer is resistant to adherence of the solder of the ball grid array package.

Solder bump array probe tip structure for laser cleaning

The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to 'stain' a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process to facilitate the detection of a specific chip structure. Further, a specific chip structure is doped with a fluorescent material during the semiconductor process. A method of the present invention comprises: providing a first and a second material; processing the first material to form a portion of a semiconductor structure; and detecting a condition of the second material to determine whether processing of the first material is complete.

Inspection methods and structures for visualizing and/or detecting specific chip structures

Disclosed is a method of manufacturing integrated circuit chips that partially joins an integrated circuit wafer to a supporting wafer at a limited number of joining points. Once joined, the integrated circuit wafer is chemically-mechanically polished to reduce the thickness of the integrated circuit wafer. Then, after reducing the thickness of the integrated circuit wafer, the invention performs conventional processing on the integrated circuit wafer to form devices and wiring in the integrated circuit wafer. Next, the invention cuts through the integrated circuit wafer and the supporting wafer to form chip sections. During this cutting process, the integrated circuit wafer separates from the supporting wafer in chip sections where the integrated circuit wafer is not joined to the supporting wafer by the joining points. Chip sections where the integrated circuit wafer remains joined to the supporting wafer are thicker than the chips sections where the integrated circuit wafer separates from the supporting wafer.

Partial wafer bonding and dicing

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Fairfax, VT, United States of America

James R Salimeno, Iii