National Semiconductor Corporation

James R Ohannes

Stephen W Clukey

Roy L Yarbrough

E David Haacke

Ernest D Haacke

A differential signaling system in which errors in signal transmission or reception, or both, can be detected to allow signal transmission to be interrupted and thereby prevent further erroneous signal transmission or reception.

Differential signaling system with signal transmission interruption following error detection

A differentially controlled variable capacitor includes two variable capacitors that are arranged effectively in parallel and receive differential input. The variable capacitors are coupled to a common node that is biased to a potential. For diode-type variable capacitors, the bias potential should ensure that the variable capacitors continue to operate as capacitors by preventing the diode device from becoming forward-biased. The differentially controlled variable capacitors are useful as tuning elements in circuits that require frequency control. A noise signal may be injected into the control signal of the variable capacitors. The effective parallel arrangement of the variable capacitors allows differential control of the effective capacitance value such that the noise signal does not alter the effective capacitance value. The differentially controlled variable capacitor is useful in circuits such as oscillators, tuned filters, and other electronic circuits that require a tuned frequency or tuned capacitance.

Differentially controlled varactor

An enhanced bipolar-transistor apparatus for protecting electronic devices from electrostatic discharge damage. The apparatus is built around a bipolar transistor coupled between a power rail and the circuit to be protected. The protection is based on the high-current-capacity path through the bipolar transistor which is opened up either by collector-to-emitter punch-through in the bipolar transistor or by the bipolar transistor going into normal conduction upon being turned on by a switch coupled to the base of the bipolar transistor. In the preferred embodiment the switch is a MOS transistor that is designed to undergo source-to-drain breakdown at a fixed threshold voltage, whereupon it activates the bipolar transistor which in turn discharges the overvoltage. In this way the advantages of the high-current-capacity bipolar transistor are obtained without the concern that fabrication vagaries will prevent the bipolar transistor from providing needed protection, such as is the situation where the punch-through phenomenon alone is relied on.

BICMOS electrostatic discharge protection circuit

An electronic switch to be used in BiCMOS circuitry when CMOS stages are controlled by logic output from (bipolar) TTL stages. Its purpose is to avoid the static leakage current I.sub.cct which can occur in a CMOS stage when the pulldown transistor is turned on while the pullup transistor is not completely turned off. This is a problem which arises when CMOS and TTL stages are coupled; the logic-high output from a TTL stage is sufficient in magnitude to turn on the CMOS pulldown transistor but not to turn off the CMOS pullup transistor. The present invention introduces an ancillary input to the subcircuit encompassing the CMOS input stage and also an ancillary output from one of the CMOS stages of the subcircuit (typically an output buffer) encompassing the TTL output stage. The ancillary output is chosen so as to provide a CMOS logic-high signal whenever the TTL stage is outputting a TTL logic-high signal. The ancillary input is connected to the control node of a switching transistor interposed between V.sub.cc and the CMOS input stage's pullup transistor. In this manner, the source of I.sub.cct is interrupted immediately after the CMOS stage is switched from pull-up mode to pull-down mode. The invention has particular applicability to latched transceivers, where the CMOS input stage is located in the latch circuit and the TTL in the tristate output buffer circuit.

I.sub.cct leakage current interrupter

A BICMOS output buffer circuit delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). A CMOS output pulldown driver transistor (Q60) sources base drive current to a relatively large current conducting bipolar primary output pulldown transistor (Q44). A relatively small current conducting CMOS secondary output pulldown transistor (Q60A) is coupled with primary current path in parallel with the primary current path of the bipolar primary output pulldown transistor (Q44) between the output (V.sub.OUT) and low potential power rail (GNDN). The control gate node of CMOS secondary output pulldown transistor (Q60A) is coupled to the control gate node of the CMOS output pulldown driver transistor (Q60) to initiate pulldown of a small sinking current before turn on of the bipolar primary output pulldown transistor (Q44) to reduce the maximum peak output noise (V.sub.OLP). A feed forward circuit capacitance is coupled between the control gate node of the CMOS output pulldown driver transistor (Q60) and base node of the bipolar output pulldown transistor (Q 44). The capacitance value is selected to pass a transient capacitive current sufficient for early turn on of the bipolar output pulldown transistor before the CMOS output pulldown driver transistor delivers sustained conduction current to reduce the maximum 'valley' output noise (V.sub.OLV).

BICMOS output buffer noise reduction circuit

A circuit to be used with bistate and tristate output buffers as a means of diverting from the output pulldown transistor Miller Current arising while the output buffer is powered down. Its purpose is to avoid loading the common bus to which the output buffer is attached, in particular under the circumstances where other output buffers on the bus are causing transitions to occur and the buffer of interest has been powered down. In its preferred embodiment the invention utilizes a MOS transistor coupled between the output pulldown transistor and the lower potential power rail of the output buffer. This MOS transistor is controlled by another MOS transistor coupled to output V.sub.OUT of the buffers. This driver transistor is controlled by the high potential power rail of the buffer and so turns on the Miller Current Discharge Transistor only when the buffer is powered down. The invention also encompasses a discharge transistor coupled to the data input V.sub.IN to ensure that the Miller Current Discharge Transistor never pulls the of the output pulldown when the buffer is in its active low state.

Power down Miller Killer circuit

An output buffer circuit (10) delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). The output buffer circuit comprises an input stage (12) coupled between a relatively quiet power supply rail (V.sub.CCQ) and a relatively quiet power ground rail (GNDQ), and an output stage (14) coupled between a relatively noisy power supply rail (V.sub.CCN) and a relatively noisy power ground rail (GNDN). A first coupling resistor (R5) is coupled between the relatively quiet and noisy supply rails (V.sub.CCQ, V.sub.CCN) for reducing V.sub.CC droop in the relatively noisy supply rail (V.sub.CCN) which in turn reduces output step in voltage during transition from low to high potential level (LH) at the output (V.sub.OUT). A second coupling resistor (R5A) is coupled between the relatively quiet and noisy ground rails (GNDQ,GNDN). The coupling resistors (R5 and R5A) have low resistance values selected for partially coupling the supply and ground rails respectively, while maintaining partial isolation for protecting input dynamic threshold levels of quiet outputs. The first coupling resistor (R5) is coupled between supply rail bond pads (20,22), while the second coupling resistor (R5A) is coupled between ground rail bond pads (30,32). The power rail bond pads (20,22) (30,32) are coupled respectively to split leads (24,25) (34,35) of a split lead leadframe merging respectively to a common V.sub.CC pin (28) and a common GND pin (38).

Partial isolation of power rails for output buffer circuits

A circuit for use in connection with tristate output buffers in order to provide concurrently for fast discharge of the output pulldown transistor base and at the same time for building in protection against reverse breakdown in the pulldown transistor. The innovation consists of providing a two discharge paths to ground for the base of the output pullup transistor. A low-capacitance path is activated only while the output buffer is in its active mode. In the preferred embodiment of the invention, this low discharge path consists of two CMOS transistors in series, one of which is controlled by the enable signal input E of the buffer circuit and the other by the data signal input V.sub.IN of the buffer circuit. The other path to ground is available whenever the data signal input V.sub.IN is low, regardless of whether the buffer is in its active or inactive mode. This other path provides discharge protection for the base of the pullup transistor for the buffer in its inactive mode, and has incorporated into it reverse breakdown protection in the form of voltage drop devices such as forward-biased diodes.

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Portland, ME, United States of America

James R Ohannes