International Business Machines Corporation

James R Mallabar

Mark William Kellogg

Bruce G Hazelzet

Brian John Connolly

Steven Alfred Grundon

John F Sweeney

A circuit and method for digitizing jitter in a high speed digital signal receives a digital signal using a comparator and supplies a clock signal to a counter. The circuit and method determine the frequency of the digital signal using the clock signal and the counter, and calculate the period of the digital signal based on the frequency (using a logic element). The method and circuit provide a linearized delay for jitter analysis based on the period of the digital signal (using a delay shift circuit) and output a delayed digital signal from the digital signal based on the linearized delay (using a measure delay circuit). The circuit and method supply the digital signal and the delayed digital signal to a programmable unit. The programmable unit comprises flip flops. The circuit and method count transitions of the flip flops within the programmable unit using the counter. The flip flops transition when the digital signal differs from the delayed digital signal. The circuit and method repeat the counting of the transitions of the flip flops for different time intervals to generate a jitter histogram of the digital signal using the logic element.

Jitter digitizer

A Synchronous DRAM memory test assembly that converts a normal PC or Workstation with a synchronous bus into a memory tester. The test assembly may be split into two segments: a diagnostic card and an adapter card to limit mechanical load on the system socket as well as permit varying form factors. This test assembly architecture supports memory bus speeds of 66 MHz and above, and provides easy access for a logic analyzer. The test assembly supports Registered and Unbuffered Synchronous DRAM products. The test assembly permits good and questionable synchronous modules to be compared using an external logic analyzer. It permits resolution of in-system fails that occur uniquely in system environments and may be otherwise difficult or impossible to replicate. The test assembly re-drives the system clocks with a phase lock loop (PLL) buffer to a memory module socket on the test assembly to permit timing adjustments to minimize the degradation to the system's memory bus timings due to the additional wire length and loading. The test assembly is programmable to adjust to varying bus timings such as: CAS (column address strobe) Latencies and Burst Length variations. It is designed with Field Programmable Gate Arrays (FPGAs) to allow for changes internally without modifying the test assembly.

Growing community of inventors

Essex Junction, VT, United States of America

James R Mallabar