Advanced Micro Devices Corporation

Standard Microsystems Corporation

Everspin Technologies, Inc.

Advanced Micro Systems, Inc.

James R MacDonald

Douglas D Gephardt

Sherman E Lee

Michael T Wisor

Dan S Mudgett

Drew Jon Dutton

Gwangwoo Johnny Choe

Stephen Cox

Henry Wurzburg

Rupaka Mahalingaiah

Rodney W Schmidt

Qadeer Ahmad Qureshi

Klaas Wortel

Rita M O'Brien

Victor F Andrade

Trevor Smith

Pankaj Bishnoi

Trenton B Henry

Guy A Stewart

Gwangwoo &ldquo;Johnny&rdquo; Choe

Romi Bose

Doug Gephardt

Govinda V Kamath

Steve Cox

Paul B Mann

The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes receiving data to be stored in a storage memory, wherein the storage memory is coupled to the memory device, wherein the memory device includes a first memory type and a second memory type different from the first memory type; storing a first copy of the received data in the first memory type; storing a second copy of the received data in the second memory type; receiving indication of a power loss to the memory device; in response to receiving indication of the power loss, copying the second copy from the second memory type to the storage memory; detecting for power restoration to the memory device after the power loss; and in response to detecting power restoration to the memory device, restoring data to the first memory type by copying data from the second memory type to the first memory type.

Systems and methods for implementing and managing persistent memory

In various embodiments, a computer system may include a computer controller to send and/or receive sideband signals to/from a USB device. In some embodiments, the USB device may include a USB controller to send/receive sideband signals to/from the computer controller. The computer controller and USB controller may allow communications between the computer system and the USB device when either of the computer system or USB device is in a low power state. The sideband signal sent between the computer system and the USB device may trigger the other of the computer system or USB device to enter a normal power state. In some embodiments, the computer controller and/or USB controller may be further coupled to a memory to buffer data to be sent to the computer system or USB device after the computer system or USB device returns to a normal power state.

Power managed USB for computing applications using a controller

A system and method for monitoring usage of peripheral devices and placing a second peripheral device in a low power state when the usage indicates that a second peripheral device is not being used. For example, if a computer system detects that a user's current typing rate indicates the user probably has both hands on a keyboard, the computer system may generate a signal to the computer mouse to enter a low power state. The computer system may use prior usage for a user to determine when current usage indicates that the second peripheral device is not being used. After the second peripheral device is placed in a low power state, the computer system may generate a signal to the second peripheral device to return to a normal power state when the computer system determines that the user no longer has both hands occupied.

Power management of computer peripheral devices which determines non-usage of a device through usage detection of other devices

A system and method for maintaining communications with a radio frequency (RF) peripheral device such as an RF input device and an RF output device. A computer may search for an RF peripheral device by transmitting a signal request on available channels until a response is received from an RF peripheral device. If the RF channel becomes busy and/or jammed, the RF peripheral device may tune into a predetermined channel while the computer scans for another channel to use. Once the computer finds a better channel, the computer may go to the predetermined channel and broadcast the new channel location to the RF peripheral device. In addition, if an RF signal arrives incomplete or corrupt, the computer may transmit a negative acknowledgement to the RF peripheral device, which may retransmit the previous RF signal.

Communication protocol for personal computer system human interface devices over a low bandwidth, bi-directional radio frequency link

A system may include a memory configured to store an attenuation waveform and control logic. The control logic is configured to receive a synchronizing signal indicative of an operating characteristic of a noise source. In response to a value of a characteristic (e.g., frequency) of the synchronizing signal, the control logic is configured to output the attenuation waveform from the memory if the attenuation waveform is associated with that value of the characteristic of the synchronizing signal. An attenuating noise generated dependent on the attenuation waveform attenuates a noise generated by the noise source.

Associative noise attenuation

A method for compiling source code to produce vector instructions, wherein parallel operands are placed in adjacent locations in memory and wherein the realignment of the operands is minimized. One embodiment generates two-element vector instructions from generalized (e.g., non-loop) source instructions. Memory locations are assigned to the corresponding operands based on the operations which are selected for parallel execution, so that parallel operations operate on data which are adjacent in memory. The memory locations are assigned in a way which minimizes realignment of the data (i.e., swapping positions of two operands.) Another embodiment comprises a software program (e.g., a vectorizing compiler) which examines a block of program code, analyzes the operators within the code and generates vectorized code in accordance with the foregoing method.

Method for generating optimized vector instructions from high level programming languages

A fully pipelined parallel multiplier with a fast clock cycle. The pipelined parallel multiplier contains three units: a bit-product matrix unit, a reduction unit, and an addition unit. The bit-product matrix is configured to receive two binary numbers, a multiplier and a multiplicand. A bit-product matrix is formed based on these two numbers. The bit-product matrix unit forms a first pipeline stage. The bit-product matrix is latched to the reduction unit using d-type latch circuits. The reduction unit includes a plurality of reduction stages, with each reduction stage acting as a pipeline stage. The reduction unit reduces the matrix down to a two-row matrix. Intermediate results are latched from one stage to the next using d-type latch circuits. The reduction unit also contains a plurality of half-adder and full-adder circuits. The final two-row matrix formed by the reduction unit is then latched to an addition unit. The addition unit includes one or more stages of addition, with each stage also acting as a pipeline stage. Carry lookahead adder (CLA) circuits are cascaded to perform the addition, with one CLA per addition stage. Results from each addition stage are latched to the next stage using d-type latch circuits. The output from the final stage is the final product of the multiplication.

Fully pipelined parallel multiplier with a fast clock cycle

A system and method for computing the cosine of an input value. The system comprises a logical processing unit and an addition unit. The logical processing unit comprises an input bus with a plurality of input lines for receiving an input angle value. The logical processing unit includes a first plurality of gates, preferably AND gates, coupled to the input bus. Each gate of the first plurality of gates couples to two or more of the input lines. The logical processing unit generates N output operands on N corresponding output buses. At least one of the output buses includes (a) at least one output line coupled to an output of one of the first plurality of gates, and (b) at least one output line coupled to one of the input lines of the input bus. The number N of output buses is greater than or equal to two. The addition unit couples to the N output buses of the logical processing unit, and is configured to perform an addition of the N binary operands provided on the N output buses. The addition unit generates a resultant number which represents the cosine of the input operand conveyed on the input bus. The input angle value is assumed to have a predetermined number of leading zeros. In general, output lines are coupled to (a) input lines, (b) outputs of gates, or (c) set equal to zero.

Cosine algorithm for relatively small angles

A system and method for evaluating one or more functions using a succession of CORDIC stages/iterations followed by a residual rotation. The succession of CORDIC stages are preferably partitioned into (a) a Z path which operates on an input angle and generates an output angle, and (b) an X/Y path which operates on an input point and generates an output point. The residual rotation rotates the output point by the output angle to generate a resultant point using a small angle approximation for sine and an accurate evaluation for sine of the output angle. The number of CORDIC stages in the succession is chosen so that the error in the coordinates of the resultant point induced by the approximation of sine is smaller than a desired amount. In particular, the number of CORDIC stages in the succession is chosen to be greater than or equal to (N&plus;1)/3 in order to guarantee N bits of precision in coordinates of the resultant point. The Z path has a propagation time which is smaller than the X/Y path. This allows the cosine computation unit to generate the cosine of the output angle prior to the time when the X/Y path generates the output point. Thus, the residual rotation may be performed immediately upon generation of the output point.

Fast CORDIC algorithm with sine governed termination

A CPU includes a real time interrupt (RTI) control unit configured to control real time interrupt capabilities of the CPU. Upon receipt of a real time interrupt signal via an RTI pin, the RTI control unit interrupts the currently executing instructions at an instruction boundary in order to execute the interrupt service routine. Instead of using the interrupt acknowledge cycles normally used to locate an interrupt vector, and then using the interrupt vector to locate an interrupt descriptor, the interrupt descriptor is stored in an RTI register coupled to the RTI control unit. In one embodiment, the CPU is configured not to save processor context upon initiation of a real time interrupt. Instead, as register resources are needed by the real time service routine, these resources are allocated. Registers allocated for real time use are indicated in the RTI register. In yet another embodiment, the CPU is configured with lockable cache lines in the instruction and data caches. An RTI bit is defined in the code and data segment descriptors for indicating whether or not the code/data within the segment is real time code/data (i.e. is used in an RTI service routine). The code/data within these segments is locked into the instruction and/or data cache. The cache replacement algorithm employed by the cache attempts to select a non-locked cache line for storing a cache line being transferred into the cache.

Real time interrupt handling for superscalar processors

A system and method for providing a microprocessor with a software accessible serial number. A plurality of programmable fuses on the processor are encoded with a value representative of a serial number. Circuitry is provided on the processor for transferring the value encoded on the programmable fuses to a machine specific or general purpose register or storage device. The machine specific or general purpose register or storage unit is software accessible.

System and method for providing microprocessor serialization using

A method and apparatus for providing a microprocessor serial number. A small, nonvolatile random access memory is packaged with the CPU die to provide a storage space for a CPU serial number which can be programmed before leaving the factory. Both the CPU die and the nonvolatile RAM die reside within the cavity of the package. Connection between the two die is provided by conventional wire bonding.

Method and apparatus for serializing microprocessor identification

A computer system is disclosed which provides for execution of real-time code from cache memory. A cache management unit provides the real-time code to the cache memory from system memory upon a initiation of a read operation by a processor. Once in cache memory, the processor executes the real-time code from cache memory instead of system memory. The cache management unit detects read hits to cache each time the processor requests an instruction of code that is stored in the cache memory. Lock bits associated with each line of cache lock the contents of the line preventing the line from being overwritten under normal cache operation in which the least most recently used cached data is replaced by presently accessed data. Alternatively, one of a plurality of cache data ways may be dedicated to storing real-time code. Real-time code stored in the dedicated data way is not replaceable and thus is locked.

Growing community of inventors

Buda, TX, United States of America

James R MacDonald