National Semiconductor Corporation

Fairchild Camera and Instrument Corp.

Fairchild Semiconductor Corporation

James R Kuo

Brian R Carey

Tuong Hai Hoang

Timothy G Moran

Shurong Zheng

SeungLi Kim

Maggie Leung

An oscillator has timing characteristics that are determined by resistor and capacitor values. The circuit comprises an astable multivibrator and a current reference. The multivibrator comprises a first and a second timing capacitor. The multivibrator is configured to produce an oscillating output signal in response to charging and discharging the first and the second timing capacitors. The current reference is configured to control the rate of change of charge of the first and second timing capacitors. The current reference is determined in part by the resistor values.

RC oscillator

Hollow heel portion for a high-heeled shoe

The crowbar current in a driver inverter, which has a pair of complementary driver transistors, is substantially reduced by adjusting the turn on and turn off times of the p-channel and n-channel driver transistors such that each driver transistor turns on after the other driver transistor has been turned off.

High-speed clock buffer that has a substantially reduced crowbar current

An apparatus for an improved output buffer includes a symmetrical pre-gain stage and a gain stage. The pre-gain stage includes a pair of matched differential amplifiers that are arranged to provide a differential intermediary signal. The gain stage is arranged to receive the differential intermediary signal and provide a single-ended output signal. The pre-gain stage differential amplifiers include transistors that are arranged as differential pairs, where each of differential pair transistors is minimally sized to provide very low capacitive loading. The pre-gain stage differential amplifiers are matched such that symmetrical amplification is obtained from the differential intermediary signal. The pre-gain stage arrangement provides for a differential intermediary signal such that common-mode noise rejection and power supply noise rejection are enhanced. The improved output buffer operates at high frequencies that are well into the gigahertz operating range, while maintaining reasonably high-gain and very low distortion in the signal symmetry.

High speed output buffer

A power-off protection circuit for an LVDS line-driver eliminates initialization problems in a local LVDS driver circuit that are caused by a remote LVDS river when the local LVDS driver is disabled. The remote LVDS driver may introduce a signal into the substrate of the local LVDS driver when the local LVDS driver is in a power-off mode. A current source in the local LVDS driver couples power from a local power supply node to the local LVDS driver when power is active. A method and protection circuit connects the substrate of the current source to the local power supply when power is active, and decouples the substrate from the local power supply when power is deactivated. The remote LVDS driver cannot cause a false power supply signal in the local LVDS driver since the conduction path is disconnected. A first switching element couples a floating substrate node in the current source to the local power supply when the power is active. A second switching element couples the floating substrate node to a bias line when power is deactivated. The first switching element is deactivated by a rising potential in the floating substrate when the local power supply is in a power-off mode. The rising potential is caused by a signal that is transmitted by the remote LVDS driver. By isolating the floating substrate from the local power, supply, false signals are eliminated and initialization problems are avoided.

Power-off protection circuit for an LVDS driver

A differential output driver circuit produces a differential output signal in response to an input data signal. The differential output driver circuit provides for a controlled edge rate in the differential output signal when the input data signal changes logic states. Control signals are generated using an adjustable delay circuit, each subsequent control signal being delayed in time from the preceding control signal by a unit delay time. The control signals control N output drivers, each of the N output drivers having an output signal coupled to the differential output signal, and each contributing a portion of the differential output signal. When the input data signal changes from one logic state to another, the differential output signal will have a defined edge rate determined by the unit delay time and the contributing portion from each of the N output drivers. In one example, the unit delay time is determined by a delay time through a buffer that has a controlled current limit. The current limit is provided by a current source that is compensated for semiconductor processing variations and temperature variations. Semiconductor processing variations are corrected by producing a current inversely proportional to a MOS transistor's trans-conductance. Since the current limit in the buffer is raised for slower transistors (lower trans-conductance), the unit delay time is compensated when the process parameters vary. The differential output driver circuit provides for minimum over-shoot, low jitter, low distortion, low signal skew, and a controlled rise and fall times over varied common mode voltages.

Digital-edge-rate control LVDS driver

A power supply regulator circuit with increased rejection of variations and noise in power supply voltage which is particularly well suited to isolating a voltage-controlled oscillator (VCO) from such power supply variations and noise. The regulator circuit uses an operational amplifier connected as a voltage follower circuit to buffer the reference voltage provided as the regulated supply potential for the VCO. This buffered voltage is also used to establish the bias voltage across a current mirror circuit which is powered by the unregulated power supply and through which the supply current for the VCO flows. This circuit topography requires no compensation capacitance and, therefore, provides increased rejection of variations and noise in the power supply voltage.

Power supply regulator circuit for voltage-controlled oscillator

A receiver includes first and second input nodes and a differential receiver having first and second inputs respectively connected to the first and second input nodes, as well as first and second outputs. First and second delay circuits are respectively connected to the first and second outputs of the differential receiver. First and second single-ended receivers each having an input are respectively connected to the first and second input nodes, the first and second single-ended receivers each having an output. Input glitch prevention circuitry includes third and fourth delay circuits that are respectively connected to the outputs of the first and second single-ended receivers and an OR gate having separate inputs that are respectively connected to the outputs of the first and second single-ended receivers and the outputs of the third and fourth delay circuits. Symmetrical delay compensation circuitry includes a fifth delay circuit that is connected to an output of the OR gate and a first AND gate having separate inputs that are respectively connected to the output of the OR gate and an output of the fifth delay circuit. Second and third AND gates each having an input are connected to an output of the first AND gate and an input is respectively connected to the outputs of the first and second delay circuits. A method of receiving differential input signals is also disclosed.

Universal serial bus receiver having input signal skew compensation

A driver which includes an output node and an output transistor connected between the output node and a first voltage reference node. A CMOS inverter is connected to a gate of the output transistor and includes a first p-channel transistor and a first n-channel transistor that have their gates connected together. A capacitance transistor is connected to the output node and the CMOS inverter and is configured to create a capacitance therebetween. A shifting transistor has its drain-source conducting path connected in series with a drain of the first p-channel transistor and a drain of the first n-channel transistor and is configured to maintain the capacitance transistor in accumulation mode. A method of driving a line includes the steps of creating a capacitance between the output node and the CMOS inverter with a capacitance transistor having its source and drain connected together, and maintaining the capacitance transistor in accumulation mode with a shifting transistor having its drain-source conducting path connected in series with a drain of the first p-channel transistor and a drain of the first n-channel transistor of the CMOS inverter.

Universal serial bus driver having MOS transistor gate capacitor

A driver for providing binary signals from a data system to a transmission line includes a data input node and an output transistor coupled between a data output node and ground. The output transistor has a gate, a source and a corresponding gate-source voltage therebetween. A first transistor is coupled to the gate of the output transistor and is responsive to signals applied to the input node. It conducts a discharge current from the gate of the output transistor for discharging the gate of the output transistor to reduce its gate-source voltage. A clamping circuit clamps the gate-source voltage of the output transistor to a first voltage level above ground to prevent the discharge current from reducing the, gate-source voltage of the output transistor to ground. In another embodiment, a supply voltage dependent current source adjusts a gate voltage of a second transistor in response to an increase in the supply voltage so that an initial charging current is maintained at a relatively constant level in response to increases in the supply voltage. A method of reducing a turn-on delay of an output transistor of a transmission line driver is also disclosed.

Transmission line driver having controllable rise and fall times with

A high speed differential data latch includes identical master and slave flip-flops. The master flip-flop is driven by a differential input data signal while both flip-flops are driven by a shared differential clock signal. Each flip-flop includes: one differential amplifier for sequentially latching the differential input data signal to provide a differential output data signal; a second differential amplifier for generating two switched supply currents from the clock signal for powering the differential data amplifier; and a third differential amplifier cross-coupled to the differential data amplifier for providing positive feedback thereto for enhancing the latching speed. The differential output data signal follows the differential input data signal during one of the differential clock states and remains latched during the other differential clock state.

High speed differential data latch

A high-speed transmission line receiver includes a basic differential amplifier stage along with a gain enhancement stage, which is generally similar to the differential amplifier stage. One of the current mirror transistors in the gain enhancement stage is connected to one of the current mirror transistors in the basic amplifier stage in such a way that the magnitude of the differential current at the output of the basic amplifier stage is increased, thereby increasing the gain of the receiver without increasing its output capacitance or the time constant of the output signal. Preferably, the transistors in the gain enhancement stage are larger than the transistors in the basic amplifier stage. Increasing the gain of the line receiver reduces the distortion which may occur as a result of the failure of the line receiver to reach a clamping voltage as the common mode of the differential input signal is increased.

High-speed transmission line receiver with wide range of common mode

A charge pump of a phase-locked loop includes a first P channel transistor and a first N channel transistor coupled to mirror a current in a constant current source. The P channel transistor and N channel transistor are formed with dimensions that match transient responses of currents through the N and P channel transistors during switching rather than matching the gains of the N and P channel transistors. In one embodiment, the channel length of the N channel transistor is twice a channel length of the P channel transistor. A second P channel transistor and a second N channel transistor connected in series with the first P and N channel transistors switch the current through the first P channel transistor and the first N channel transistor respectively. The second P channel transistor and the second N channel transistor have matched gate-drain capacitances so that they have the same switching speed. A first capacitor coupled between the gate of the first P channel transistor and a supply voltage and a second capacitor coupled between the gate of the first N channel transistor and a reference voltage reduce the effect that jitter in the supply and reference voltages has on the charge pump.

Charge pump with near zero offset current

A driver for providing binary signals from a data system to a transmission line is disclosed. A first n-channel transistor has its drain coupled to the transmission line and its source coupled to ground. The channel of the first n-channel transistor has a width that is greater than its length. A first inverter stage conducts current from a first voltage supply to the gate of the first n-channel transistor in order to switch the first n-channel transistor into a conductive state and conducts current from the gate of the first n-channel transistor to ground in order to switch the first n-channel transistor into a non-conductive state. A discharge circuit provides a discharge path from the gate of the first n-channel transistor to ground during a discharge time period and then removes the discharge path at the end of the discharge time period. A temperature compensation circuit may be coupled to the first inverter stage to adjust the level of current conducted to the gate of the first n-channel transistor and the level of current conducted from the gate of the first n-channel transistor to compensate for variations in temperature.

CMOS bus and transmission line driver having compensated edge rate

A temperature compensation circuit is disclosed that includes a first field-effect transistor (FET), a second FET, a resistor, and current generating circuitry. The second FET has a larger current conducting channel than the current conducting channel of the first FET, and the gate of the second FET is coupled to the gate of the first FET. The resistor is coupled between a first node that is common with the source of the first FET and a second node that is common with the source of the second FET. The current generating circuitry generates and maintains substantially equal drain currents in the first and second FETs. In an alternative embodiment, a positive temperature coefficient current generation stage that includes a first FET causes a first current conducted by the channel of the first FET to increase when temperature increases and decrease when temperature decreases, and a programmable current transfer and modification stage generates a third current that may be selectively programmed to be any one of a plurality of values that are linearly proportional to the first current conducted by the channel of the first FET.

Growing community of inventors

Cupertino, CA, United States of America

James R Kuo