Freescale Semiconductor,inc.

James R Griffiths

David M Gonzalez

Elie A Maalouf

Darrel R Frear

Neil T Tracht

Tien Yu T Lee

Lizabeth Ann A Keser

An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.

Redistributed chip packaging with thermal contact to device backside

A power amplifier for use in a radio frequency (RF) transmitter or other device exhibits improved protection from voltage standing wave ratio (VSWR) issues emanating from avalanche currents. The amplifier circuit includes a power transistor having a base terminal, and a mirror transistor having a collector terminal and a base terminal. The base terminal is coupled to the collector terminal of the mirror transistor to thereby provide a bias current to the base terminal of the mirror transistor. The base terminal is also coupled to the base terminal of the power transistor to thereby form a base bias feed node for a current mirror arrangement. A static or variable impedance is coupled to the base bias feed node to sink current and to thereby maintain the proper bias current at the base terminal of the mirror transistor to thereby continue operation of the mirror transistor while avalanche conditions exist.

Power amplifiers having improved protection against avalanche current

A method () is described for an electronic assembly (). An electronic die () with a sacrificial layer () on its back () and electrical contacts () on its front () is temporarily attached by its front () to a substrate (). The back () is over-molded by a first material () extending over the substrate (). The substrate () is removed leaving the die contacts () and the first material () exposed. Interconnect layer(s) () are provided over the first material () and the die (), electrically coupled to the contacts (). Further components () can be coupled to the upper-most interconnects (). A second material () is over-molded over the components () and upper-most interconnects (). Thinning the first material () exposes the sacrificial layer () for removal. The die back () and vias () in the first material () extending to the first interconnect layer (-) laterally outside the die () are filled with a conductor (), providing single surface electrical and thermal contact (--), separated by just the die thickness from heat generating regions of the die ().

Removable layer manufacturing method

Systems and methods are described for improving the startup linearization of a power amplifier. A bias network is provided to generate a bias signal during amplifier startup, and the amplifier is configured to produce an output signal in response to the input signal and the bias signal. A variable impedance is provided to couple the input signal and the output signal in parallel with the amplifier. A controller is configured to apply a weighting function to the variable impedance over at least a startup phase of the amplifier system. By applying a non-linear or other weighting function to the variable impedance during startup, the gain of the amplifier can be controlled to thereby extend a time period over which the output power of the amplifier increases in a generally linear manner toward an operating level.

Power amplifiers having improved startup linearization and related operating methods

An RF transmitting device () includes an RF amplifier () formed having components formed on a common semiconductor substrate (). RF amplifier () includes MOS transistors () and () and an RF choke () stacked between a ground node () and a Vnode (). Transistors () and () are directly connected together and are biased by a control terminal bias network () so that the voltages appearing across their conduction terminals are about equal. Control terminals () and () of transistors () and () are driven by in-phase versions of an RF input signal ().

Growing community of inventors

Chandler, AZ, United States of America

James R Griffiths