Compaq Computer Corporation, Inc.

Advanced Micro Devices Corporation

James R Edwards

David J Maguire

Dwight D Riley

Gregory N Santos

Robert A Lester

Jeffrey C Stevens

Richard S Lin

Christopher C Wanner

David J Delisle

John Edward Larson

Michael J Collins

William C Hallowell

James R Reif

Todd J DeSchepper

Marshall A Dawson

Scott B Hoot

Kevin B Tanguay

David W Frodin

A memory system () includes a plurality of memory devices () adapted to be coupled to an interface (), an indicator () for indicating a type of the plurality of memory devices (), and an override circuit () having a first terminal adapted to be coupled to the interface (), a second terminal coupled to the plurality of the memory devices (), and a control input for receiving a control signal. The override circuit () is responsive to the control signal to alter an operation of the memory system ().

Memory system such as a dual-inline memory module (DIMM) and computer system using the memory system

An apparatus handles long latency interrupt signals in a computer which posts I/O write operations. The apparatus includes a posting buffer for posting write operations and circuitry for ensuring that End-of-Interrupt (EOI) write operations (and other interrupt controller directed I/0 operations) are properly synchronized to prevent false interrupts from reaching the processor. Upon receipt of the EOI write operation, the apparatus verifies that the posting buffer is empty before it imposes a pre-determined delay to ensure sufficient time for the cleared the interrupt signal to be transmitted over the interrupt serial bus. Next, the apparatus checks the interrupt serial bus for activities. If the interrupt serial bus is idle, the EOI write operation is issued to the interrupt controller. Alternatively, the apparatus waits until the serial bus becomes inactive for two back-to-back cycles before allowing the EOI write operation to be issued to the interrupt controller. The back-to-back wait requirement prevents false interrupts from being generated in the event that the cleared interrupt may have missed its transmission window over the current interrupt serial bus cycle, or the event that the cleared interrupt was delayed by any interrupt serial bus transmission latencies.

Long latency interrupt handling and input/output write posting

A method for hot docking and hot undocking a portable computer and a docking station. The portable computer and docking station are physically coupled via a shared PCI bus and an expansion connector. Varying length pins in the expansion connector generate docking and undocking handshaking signals used by microcontrollers in the portable computer and docking station. The portable computer and docking station are functionally connected via low onresistance switches located in the portable computer. Following a docking event, closure of the switches connects the portion of the shared PCI bus in the docking station with the PCI bus in the portable computer. When the switches are open, the PCI busses are functionally isolated. Both the portable computer and the docking station also include a local arbiter for arbitrating and granting bus control requests from devices coupled to the shared PCI bus. These local arbiters may be placed into an idled state by either the operating system (through system BIOS) or by the microcontrollers. The arbiters are idled during docking and undocking events in order to inhibit bus cycles on the PCI bus, thereby preventing cycles from being lost. Following completion of a hot docking or undocking event, Plug-and-Play system reconfiguration is carried out so that all system resources may be recognized and properly utilized by the operating system.

Computer system implementing hot docking and undocking capabilities by

A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

Interfacing direct memory access devices to a non-ISA bus

An arbitration scheme for a computer system having multiple arbiters for arbitrating access to a plurality of buses. In the preferred embodiment, a computer system is divided into a detachable laptop portion and an expansion base unit coupled through a shared PCI bus. Each of the two portions of the computer system includes separate PCI arbitration circuitry for arbitrating requests for the PCI bus from potential PCI and ISA bus masters. Included within the laptop portion of the computer system is a top level arbiter that determines whether the PCI arbiter in the laptop or expansion base unit has access to the PCI bus. Either PCI arbiter normally must receive a grant from the top level arbiter before it runs a cycle. While the laptop computer is docked, the top level arbiter selects between the PCI arbiters on an essentially time multiplexed basis. While the expansion base and laptop computer are undocked, the top level arbiter grants bus access to the laptop PCI arbiter.

Circuit for handling distributed arbitration in a computer system having

An apparatus handles long latency interrupt signals in a computer which posts I/O write operations. The apparatus includes a posting buffer for posting write operations and circuitry for ensuring that End-of-Interrupt (EOI) write operations (and other interrupt controller directed I/O operations) are properly synchronized to prevent false interrupts from reaching the processor. Upon receipt of the EOI write operation, the apparatus verifies that the posting buffer is empty before it imposes a pre-determined delay to ensure sufficient time for the cleared the interrupt signal to be transmitted over the interrupt serial bus. Next, the apparatus checks the interrupt serial bus for activities. If the interrupt serial bus is idle, the EOI write operation is issued to the interrupt controller. Alternatively, the apparatus waits until the serial bus becomes inactive for two back-to-back cycles before allowing the EOI write operation to be issued to the interrupt controller. The back-to-back wait requirement prevents false interrupts from being generated in the event that the cleared interrupt may have missed its transmission window over the current interrupt serial bus cycle, or the event that the cleared interrupt was delayed by any interrupt serial bus transmission latencies.

A method for hot docking and hot undocking a portable computer and a docking station. The portable computer and docking station are physically coupled via a shared PCI bus and an expansion connector. Varying length pins in the expansion connector generate docking and undocking handshaking signals used by microcontrollers in the portable computer and docking station. The portable computer and docking station are functionally connected via low on-resistance switches located in the portable computer. Following a docking event, closure of the switches connects the portion of the shared PCI bus in the docking station with the PCI bus in the portable computer. When the switches are open, the PCI busses are functionally isolated. Both the portable computer and the docking station also include a local arbiter for arbitrating and granting bus control requests from devices coupled to the shared PCI bus. These local arbiters may be placed into an idled state by either the operating system (through system BIOS) or by the microcontrollers. The arbiters are idled during docking and undocking events in order to inhibit bus cycles on the PCI bus, thereby preventing cycles from being lost. Following completion of a hot docking or undocking event, Plug-and-Play system reconfiguration is carried out so that all system resources may be recognized and properly utilized by the operating system.

System incorporating hot docking and undocking capabilities without

A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

Apparatus and method for positively and subtractively decoding addresses

Computer system utilizing two ISA busses coupled to a mezzanine bus

A dual-master data storage interface is disclosed which flexibly configures and connects data storage drives in the portable computer to optimize performance when the portable computer is operating in a stand-alone mode and to optimize accessibility to additional data storage drives when the portable computer is docked with an expansion unit. When the portable computer operates as a stand-alone unit (i.e., not docked to the expansion unit), each drive on the portable is configured to operate as a master drive to optimize performance. When the portable computer docks with the expansion unit, the first channel on the portable computer is connected via switches to both drives of the portable computer, while the second channel on the portable computer is disconnected. Further, the first data storage drive is configured as a master and the second data storage drive is configured as a slave drive on the portable computer side. Correspondingly, the drives located on the expansion base unit are reconfigured and remapped as master and slave drives on the second channel on the expansion base unit, while the first channel on the expansion base unit is disconnected.

Reconfigurable dual master IDE interface

A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-volt and 5-volt components connected to the PCI bus.

Growing community of inventors

Longmont, CO, United States of America

James R Edwards