Hewlett-packard Development Company, L.p.

Intel Corporation

James R Callister

Dale Calvin Morris

Eric R Delano

Rohit Bhatia

Stephen R Undy

James Earl McCormick, Jr

Thomas L Vaden

Shawn Kenneth Walker

Scott J Norton

Teresa Louise Johnson

Richard Eugene Hank

Mark M Gibson

Susith Rohana Fernando

Thomas A Heynemann

A processing device includes a processor to generate a plurality of events, an interface circuit coupled to the processor comprising one or more multiplexers to select events from the plurality of events, and a tracker logic coupled to the interface circuit to perform a quality of service (QoS) measurement based on the selected events.

Mechanism to monitor quality of service

Systems, methodologies, computer-readable media, and other embodiments associated with ordering instructions are described. One exemplary system embodiment can include an analysis logic configured to analyze executable instructions from an executable program. A re-write logic can be configured to re-order selected load instructions within the executable program based on latency times for the selected load instructions.

Systems and methods for re-ordering instructions

Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.

Mitigating context switch cache miss penalty

Systems, methodologies, media, and other embodiments associated with acquiring instruction addresses associated with performance monitoring events are described. One exemplary system embodiment includes logic for recording instruction and state data associated with events countable by performance monitoring logic associated with a pipelined processor. The exemplary system embodiment may also include logic for traversing the instruction and state data on a cycle count basis. The exemplary system may also include logic for traversing the instruction and state data on a retirement count basis.

Acquiring instruction addresses associated with performance monitoring events

In an embodiment of the invention, a method for dynamic hardware multithreading, includes: using a hardware halt function or a hardware yield function in a processor core in order to enable or disable a hardware thread that shares the core; wherein the hardware thread is disabled by placing the hardware thread in a halt state or yield state, and allowing another hardware thread to utilize the core.

Dynamic hardware multithreading and partitioned hardware multithreading

A method for prefetching instructions into cache memory using a prefetch instruction. The prefetch instruction contains a target field, a count field, a cache level field, a flush field, and a trace field. The target field specifies the address at which prefetching begins. The count field specifies the number of instructions to prefetch. The flush field indicates whether earlier prefetches should be discarded and whether in-progress prefetches should be aborted. The level field specifies the level of the cache into which the instructions should be prefetched. The trace field establishes a trace vector that can be used to determine whether the prefetching operation specified by the operation should be aborted. The prefetch instruction may be used in conjunction with a branch predict instruction to prefetch a branch of instructions that is not predicted.

Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted

Growing community of inventors

San Jose, CA, United States of America

James R Callister