Analog Devices,inc.

Fairchild Camera and Instrument Corp.

Precision Monolithics, Inc.

James R Butler

Douglas S Smith

A double-folded cascode operational amplifier capable of operating with rail-to-rail common mode inputs includes two differential input transistor pairs of opposite conductivity, with an associated current source and input resistor pair for each pair of input transistors. Its gain stage includes two interconnected pairs of folded cascode gain transistors that are connected to the two pairs of input resistors so that a change in the differential input signal produces a corresponding change in the gain stage output via the resistors. An output stage includes transistor-resistor circuitry to bias a pair of output transistors in opposite directions and produce a net amplifier output at their junction. The gain transistor voltages are balanced by a voltage shifting circuit to inhibit input voltage offsets.

Balanced double-folded cascode operational amplifier

A bipolar micro-power rail-to-rail operational amplifier has a low complexity output stage that provides a high ratio of load current to no load idle current. The output stage includes first and second output transistors of opposite conductivities whose current circuits are connected in series at the output terminal between high and low voltage supplies. A control transistor responds to the drive voltage at its base by modulating the base-emitter voltages of the first output transistor and a gain transistor in opposite directions to modulate their respective output and gain currents. A regenerative current source supplies current to the gain transistor by returning the gain current in a regenerative feedback loop to its emitter so that the current source idles at a low gain current but is capable of supplying much higher gain currents. A voltage element responds to the gain current by applying a control voltage to the base of the second output transistor so that the output transistors' output currents are unbalanced thereby generating an output current at the output terminal.

Bipolar micro-power rail-to-rail amplifier

Method for controlling an output stage of a bipolar micro-power

A double-folded cascode operational amplifier capable of operating with rail-to-rail common mode inputs includes two differential input transistor pairs of opposite conductivity, with an associated current source and input resistor pair for each pair of input transistors. Its gain stage includes two interconnected pairs of folded cascode gain transistors that are connected to the two pairs of input resistors so that a change in the differential input signal produces a corresponding change in the gain stage output via the resistors. An output stage includes transistor-resistor circuitry to bias a pair of output transistors in opposite directions and produce a net amplifier output at their junction.

Double-folded cascode operational amplifier

The gain of a folded cascode operational amplifier is enhanced by connecting the current circuits of added compensation transistors to supply the current circuits of pre-existing gain transistors. Changes in the current through the primary gain transistor resulting from a change in the output load produce approximately equal changes in the base currents of both the primary gain and primary compensation transistors. The change in the compensation transistor's base current is transmitted through the amplifier circuitry to supply the change in the gain transistor's base current, rather than forcing a change in the input voltage differential to supply this current. The differential input signal is thus less sensitive to changes in the output, resulting in higher transconductance and gain. Providing a similar compensation loop for a second gain transistor through the second compensation transistor produces a circuit balance that lowers both the circuit's offset voltage, and the temperature dependence of the offset voltage.

Folded cascode operational amplifier with gain enhancing base current

A wide dynamic range transconductance stage has two branches, each branch being composed of a plurality of transconductance circuit paths. Each circuit path has a greater transconductance than the other circuit paths for its branch within a respective sub-range of the input signal range for the stage as a whole, with each path dominating the other paths for its branch within its respective sub-range. The overall bandwidth for the stage, its g.sub.m, its noise characteristics and its input voltage range are enhanced as a result. Bandwidth and slew rate may be independently optimized by the designer. Two paths are used for each branch in the preferred embodiment, with one path consisting of a bipolar transistor and the other path either a field effect transistor or a resistor degenerated bipolar transistor. Multiple paths may be used based on the same principle.

Wide dynamic range transconductance stage

A differential input circuit has an input stage with a pair of differentially biased input transistors connected to supply current through respective load impedances, and a gain stage with a second pair of transistors connected to supply additional currents to the load impedances to keep the impedance currents constant over variations in the input voltage levels. A cross-coupled cascode circuit connected between the gain stage transistors and the load impedances compensates for inaccuracies in the load impedance currents which occur during dynamic operation of the circuit, and thus enhances gain, linearity and the current transfer efficiency between the two stages.

High efficiency cross-coupled folded cascode circuit

A JFET differential amplifier stage in which the gate-drain voltage of each input JFET is kept at least as great as the pinchoff voltage (V.sub.p), but preferably close to V.sub.p so as to reduce the effects of impact ionization and generation currents on the amplifier's input bias current. The input JFETs are cascoded with another pair of JFETs, and the gate-source circuits for the JFETs of each branch are connected in series with the gate-source circuit of an additional JFET between the gates and drains of the input JFETs. The additional JFET is supplied with a current that is substantially less than I.sub.DSS, and thus develops a significant portion of the necessary gate-drain voltages for the input JFETs. This enables a significant net reduction in the chip surface area occupied by the stage.

Area efficient cascode driver circuit

An active load circuit for operational amplifiers and the like is described which provides an improved common mode rejection ratio and common mode voltage range, and alleviates transistor saturation and cut off problems during maximum slew rates. Drive currents from the operational amplifier or other circuit are transmitted directly through respective load resistors, thereby reducing voltage offsets which degrade common mode rejection ratio. At the same time the absolute voltage levels at the operational amplifier or like circuit are reduced, thereby increasing the common mode voltage range. A pair of active load transistors are supplied with current from current sources independent of the amplifier transistors, and deliver their respective currents to the same resistors which receive the amplifier currents. An output is taken from one of the load transistors without connecting to either of the amplifier transistors.

JFET active load input stage

A JFET differential amplifier stage in which the gate-drain voltage of each JFET is kept at least as great as the pinchoff voltage (V.sub.p), but preferably close to V.sub.p so as to reduce the effects of impact ionization and generation currents on the amplifier's input bias currents. The JFETs are supplied with currents which force their gate-source voltages to at least 0.5 V.sub.p. A second pair of JFETs are cascoded with the first pair and also develop gate-source voltages of at least 0.5 V.sub.p. The gate-source terminals of the second pair are connected in a loop with the source-drain terminals of the first pair, thereby forcing the gate-drain voltages of the first pair to at least V.sub.p, the minimum voltage necessary to hold the first pair in a desired saturated state. A third pair of JFETs is connected to buffer the first pair from capacitances developed at the gates of the second pair without effecting the AC operation of the circuit.

JFET Differential amplifier stage with method for controlling input

In a bias circuit including at least a pair of bipolar transistors interconnected to function as active loads, two junction field effect transistors are interconnected such that the source of one transistor is connected to the emitter of the first of the pair of bipolar transistors and the source of the second junction field effect transistor is connected to the emitter of the second of said bipolar transistors, and the gate electrodes of the first and second junction field effect transistors are electrically connected to each other and to the drain electrodes of both the first and second junction field effect transistors. Alternatively, the drain electrodes of the first and second junction field effect transistors are connected to a common bus and the gate electrodes are connected to a low impedance node.

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San Jose, CA, United States of America

James R Butler