Other

Intelect Communications, Inc.

Teraforce Technology Corporation

Intelect Systems Corporation

Terraforce Technologies Corp.

James R Bartlett

Michael C Greim

Winthrop W Smith

Robert L Hutchings, Ii

Jay T Labhart

A quad-processor arrangement having 6 communications paths, one path between each of every possible pair of processors. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. The communications paths are controlled and interfaced to the processors through field programmable logic, which allows the board to be configured both statically and dynamically to optimize the data transfer characteristics of the module to match the requirements of the application software. The programmable logic may be configured so that the module emulates other existing board architectures in order to support legacy applications.

Multi-processor architecture for parallel signal and image processing

A multi-processor system includes a global bus ( ) having associated therewith a global address space with a plurality of processor nodes ( ) associated therewith. Each of the processor nodes ( ) has a CPU ( ) associated therewith which interfaces with a local bus. The local bus has a local address space associated therewith. A dual port SRAM (DPSRAM)( ) is provided for interfacing between the global bus ( ) and the local bus ( ). Each DPSRAM ( ) for each processor core ( ) has a defined address space within the global bus address space. Whenever any of the global resource writes to the particular processor node ( ), it is only necessary to address the designated DPSRAM ( ) and transfer data thereto. The act of transferring the data thereto will generate an interrupt to the associated CPU ( ) which will then cause it to read the received data on the local bus by addressing its associated DPSRAM ( ). This results in only a single access cycle for transfer of the block of data from the global resources to the designated CPU ( ).

DSP with distributed RAM structure

A multi-processor system includes a global bus ( ) with a global address space and a plurality of processor nodes ( ). Each of the processor nodes ( ) has a CPU ( ) interfaced with a local bus having a local address space. A dual port SRAM (DPSRAM) ( ) is provided for interfacing between the global bus ( ) and the local bus ( ). Each DPSRAM ( ) for each processor core ( ) has a defined address space within the global bus address space. Whenever any of the global resource writes to the particular processor node ( ), it is only necessary to address the designated DPSRAM ( ) and transfer data thereto. The act of transferring the data thereto will generate an interrupt to the associated CPU ( ) which will then cause it to read the received data on the local bus by addressing its associated DPSRAM ( ). This results in only a single access cycle for data transfer. Each of the CPU's ( ) can communicate directly with another of the CPU's ( ) through an interprocessor communication network. This network includes a Bi-FIFO ( ). The CPU ( ) is operable to interface with a predefined type of memory having a defined memory access protocol different from that of the Bi-FIFO ( ). Therefore, a translator circuit is required to convert memory access commands and data flow to a compatible format with that of Bi-FIFO ( ). This includes a programmable bi-directional pipeline circuit ( ) and also a predecode circuit ( ) to allow selection of one of a plurality of Bi-FIFOs to allow the CPU ( ) to communicate with different Bi-FIFOs within the same memory space.

DSP intercommunication network

A multi-processor system includes a global bus ( ) having associated therewith a global address space with a plurality of processor nodes ( ) associated therewith. Each of the processor nodes ( ) has a CPU ( ) associated therewith which interfaces with a local bus. The local bus has a local address space associated therewith. The global bus ( ) has associated therewith an arbiter ( ). Each of the processing nodes interfaces with a global register ( ) which is operable to contain paging registers for each of the files. A portion of the memory space in the processing nodes is paged over to the global address space. To facilitate the upper address bits of the global address space they are stored in a paging register and then the arbiter ( ) selects these upper address bits for output to the bus. The lower address bits are provided by the particular processor node that is accessing the global address space.

Paging method for DSP

A multi-processor system is provided having a processor array configured of a plurality of CPUs (20) that are disposed on a global bus (14). A VEM interface (18) is provided for interfacing between the global bus (14) and a system bus (12). Interrupts that are generated on the system bus (12) are mapped to the CPUs (20) through an interrupt controller (82). The interrupt controller (82) is operable to receive multiple interrupts and store these interrupts and their associated interrupt vectors. After storage, a gating register associated with each CPU (20) is examined to determine which interrupts are serviced by a particular CPU (20). If an interrupt is received that is to be serviced by one or more of the CPUs (20), then an external interrupt is generated for that CPU (20). Once the external interrupt is generated, the CPU will then examine a flag register associated therewith, which flag bits are set only if the interrupt controller (82) has determined that the CPU (20) is to receive the interrupt in accordance with the contents of the gating registers. The CPU (20) will then service the particular interrupts directed thereto by accessing the stored interrupt vectors. Once all CPUs (20) that are to service an interrupt have retrieved the interrupt vector, an acknowledgment signal is sent back to the system bus (12).

DSP interrupt control for handling multiple interrupts

A kit and a process for use in making a highly personalized memento wherein the kit includes a supply of impression material and plaster material so that, the impression material, when combined with water, may be applied directly to the hands or feet of a subject creating an impression which, when removed from the subject a mixture of the plaster material and water may be poured into the impression and allowed to set, creating a reproduction of the subjects hand prints or footprints which may then be affixed to a plaque member along with a photograph of the subject and a nameplate on which is recorded information about that subject.

Kit and process for use in making a personalized memento

A triangular frame assembly is disclosed for supporting a safety barrier of boards above the edge of a roof during construction. The triangular assembly employs pivotal connections between a base and a lower stanchion member, between the base and a diagonal brace, and between the diagonal brace and an upper stanchion member telescopically connected to the lower stanchion member. The angle between the stanchion and the base can be adjusted to accommodate a wide range of roof pitches by varying the telescopic engagement of the upper and lower stanchion members. The range of roof pitch angles for which the frame assembly can be used is increased by making the upper stanchion member invertable, adapting both ends thereof to alternatively telescopically engage the lower stanchion member, and by providing for an off-center brace connection to the upper stanchion member. A variation of the invention provides for a rigid triangular frame secured below the eave of a roof for supporting a stanchion extending above the eave.

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Plano, TX, United States of America

James R Bartlett