Lsi Logic Corporation

Nantero, Inc.

James R B Elmer

Peter Austin Burke

Eric J Kirchner

Shiqun Gu

David W Daniel

Byung-Sung Kwak

Sey-Shing Sun

Hemanshu D Bhatt

Wai Lo

Verne C Hornback

Hong Lin

Colin D Yates

Richard J Carter

Ann I Kang

A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

Self-aligned cell integration scheme

A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches. A target thickness of the insulating material necessary to leave the trenches substantially filled to a top surface of the field of polish stop material is calculated. The substrate is polished until a first thickness of the insulating material in the trench of the first metrology site is no more than the target thickness. A second thickness of the insulating material in the trench of the second metrology site is measured, and values based on the first thickness and the second thickness are monitored as the polishing process parameters for the integrated circuit structure.

Integrated circuit process monitoring and metrology system

An apparatus for aligning a mask having an image and at least one complimentary alignment mark to a substrate having a first surface and a substantially opposing second surface. The substrate further has at least one alignment mark on the second surface. A mask support supports the mask in proximity to the first surface of the substrate. A substrate support supports the substrate with the first surface in proximity to the mask. An alignment means aligns the at least one alignment mark on the second surface of the substrate to the at least one complimentary alignment mark on the mask. An exposure source projects the image of the mask onto the first surface of the substrate, and a controller controls the mask support, substrate support, alignment means, and exposure source.

Process independent alignment marks

A method for characterizing overlay errors between at least a first and a second mask layer for an integrated circuit. A first primary alignment structure is formed in a first position of the inter-layer region around the first mask layer, and a first secondary alignment structure is formed in a second position of the inter-layer region around the first mask layer. Similarly, a second primary alignment structure is formed in a first position of an inter-layer region around the second mask layer, and a second secondary alignment structure is formed in a second position of the inter-layer region around the second mask layer. The first mask layer and the second mask layer are exposed onto a photoresist coated substrate with a first exposure and a second exposure, where the first position of the first primary alignment structure during the first exposure generally aligns with the second position of the second secondary alignment structure, and the second position of the first secondary alignment structure during the second exposure generally aligns with the first position of the second primary alignment structure. The photoresist on the substrate is developed, and offsets between the first primary alignment structure and the second secondary alignment structure are measured, and offsets between the second primary alignment structure and the first secondary alignment structure are also measured, to determine the overlay errors.

Reticle overlay correction

An integrated circuit substrate having a first surface for receiving a series of aligned layers during the creation of the integrated circuit, and a second surface disposed substantially opposite the first surface, where the second surface has at least one alignment mark for aligning the series of aligned layers one to another during creation of the integrated circuit. An apparatus for aligning a mask having an image and at least one complimentary alignment mark to a substrate having a first surface and a substantially opposing second surface, where the substrate has at least one alignment mark on the second surface.

A method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode layer is the patterned. LDD regions are formed using an ion implantation process, thereby creating damaged portions of the high k layer. A first portion of the damaged portions of the high k layer are removed, thereby defining a gate structure, and leaving remaining portions of the damaged portions of the high k layer. Sidewall spacers are formed adjacent the gate structure. Source/drain regions are formed using an ion implantation process, thereby further damaging the remaining portions of the damaged portions of the high k layer. The remaining portions of the damaged portions of the high k layer are then removed.

Selective high k dielectrics removal

A reticle includes multiple different layer patterns selected from a group comprising same circuit layer patterns and different circuit layer patterns. The layer patterns are positioned on the reticle within borders and within a portion of a defined x by y array on the reticle. The reticle is used to produce an integrated circuit of a single design or integrated circuits of multiple designs.

Multi pattern reticle

A method for forming an alignment feature on a substrate. The alignment feature is of the type concurrently formed with an electrically conductive layer overlying an electrically nonconductive layer having vias. The vias are filled with an electrically conductive material, and the alignment feature has a smaller aspect ratio than the vias. The alignment feature is not filled with the electrically conductive material when a first amount of the electrically conductive material, sufficient to just fill the vias, is deposited on the substrate. The first amount of the electrically conductive material within the alignment feature is not sufficient to prevent the alignment feature in the electrically conductive layer from distorting, and thereby reducing the effectiveness of the alignment feature. The improvement is in depositing an additional amount of the electrically conductive material on the substrate. The additional amount is more than the first amount that is just sufficient to fill the vias, and fills the alignment feature to a level sufficient to prevent the alignment feature in the electrically conductive layer from distorting and reducing the effectiveness of the alignment feature.

Growing community of inventors

Vancouver, WA, United States of America

James R B Elmer