Intel Corporation

James Q Mi

Albert Fazio

Gregory E Atwood

Albert Teng

Vishesh M Parikh

Johnny Javanifard

Dennis Dilley

Millind Mittal

Paul D Ruby

A computer system includes an interface and a processor. The interface is adapted to receive a request from another computer system for identification of the first computer system. The adapter also furnishes a hash value that identifies the first computer system to the other computer system. The processor is coupled to the interface and is adapted to encrypt an identifier that identifies the first computer system with a key associated with the other computer system to provide the hash value.

Computer system identification

A method and apparatus for enabling hardware platform identification while ensuring privacy protection. The apparatus comprises a computer-readable medium that stores computer-executable instructions. Those instructions, when executed by a microprocessor, cause an expected hash value, which is derived from a key and a first identifier for a computer system; to be compared with a hash value, which is derived from the key and a second identifier for a computer system. A microprocessor for executing those instructions may comprise an identifier that identifies the microprocessor, and embedded instructions for comparing a hash value, derived from the identifier and a key, to an expected hash value.

Method and apparatus for hardware platform identification with privacy protection

A system and method for controlling access to an object. The system stores an object and a processor identifier. The system includes a verification agent that can access information embedded in a processor and then calculate from that embedded information a value that may be compared with the stored processor identifier. A comparison agent is used to compare that value with the processor identifier to determine whether the processor corresponds to the processor identifier. If the value that the verification agent returns matches the processor identifier, then the computer grants the user access to the object.

System and method for using internet based caller ID for controlling access to an object stored in a computer

A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

Method and circuitry for storing discrete amounts of charge in a single

A method for programming an array of memory cells wherein each cell may be placed in more than two states. The method comprises the steps of 1) selecting a plurality of different programming voltage levels wherein each programming voltage level is associated with a corresponding one of a plurality of states, and 2) applying a plurality of programming pulses to selected subsets of the array of memory cells, wherein each programming pulse has one of the programming voltage levels and one of a corresponding plurality of pulse widths such that each of the memory cells of a corresponding one of the selected subsets are programmed directly to a corresponding one of the plurality of states by a corresponding programming pulse.

Programming flash memory using strict ordering of states

A method for storing a charge on memory devices which includes the steps of providing a first charging pulse to a memory device to charge the device to a first level less than a final level; testing the value of the charge to determine whether the charge is greater than the first level; if the value of the charge is less than the first level, providing a second set of charging pulses to the memory device, each of the pulses of the second set of pulses having a duration which is a fraction of the duration of the first pulse and a value sufficient to charge the device to the first level; testing the value of the charge to determine whether the charge is greater than the first level after each pulse of the second set of pulses; and once the charge has tested greater than the first level, providing a third set of charging pulses to terminals of the memory device, each of the pulses of the third set of pulses having a duration which is a fraction of the duration of the pulses of the second set of pulses and a value such that the charge furnished by each pulse is approximately equal to an allowable variation of the charge from the final value.

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Sunnyvale, CA, United States of America

James Q Mi