Amazon Technologies, Inc.

James Paul Rivers

Scott Andrew Emery

Colin John Whittaker

Alan Michael Judge

Ke Zhang

Alaa Adel Mahdi Hayder

Tahsin Erdogan

Poorya Saghari

Joshua Benjamin Levinson

Julien Ridoux

Leonid Livak

Paul Yu

Mark Kamichoff

Yuan Yuan

Abhishek Vinayak Naik

Chinchu Merine Joseph

Shrawan Chittoor Surender

Shriram Srinivasan

A clock signal in a clock distribution network is transmitted using network packets with the clock signal embedded within a bit of the network packets. The network packets can include a preamble used to create phase alignment between a timing pulse and a bit position of a Start of Frame Delimiter (SFD) within the packet. The clock signal associated with the packet occurs when the SFD is detected. In one example, the SFD is detected when two consecutive bits of equal value are received and the timing of the clock signal is such that the clock signal occurs when the second consecutive bit is received. By including a clock signal within a packet, additional information can be transmitted with the clock signal. For example, authentication and validation information can be included, a time stamp, a message type, a frame check sequence, a clock status, a number of hops from the root, etc.

Transmitting clock signals in network packets

A host-to-ToR switch advertisement protocol can be used at a data center network edge to receive IP advertisements from hosts and convey ToR switch availability status (e.g., in service, intentionally out of service, or unintentionally out of service) back to hosts and vice versa. The host server computers can have the ability to advertise an arbitrary number of IPv4 or IPv6 prefixes to the network through the ToR switches. A single host server computer can leverage multiple instances across multiple ports to the same switch or different switches to implement load balancing (e.g., equal cost multipath (ECMP)) and fault tolerance. The host server computers benefit from an increased availability by receiving network traffic via multiple ToR switches, a single ToR switch with multiple links, or a combination of both.

Network rack of host server computers with increased network availability

A clock signal in a clock distribution network is transmitted using network packets with the clock signal embedded within a bit of the network packets. The clock signal is adjusted to account for propagation delay in transmitting the clock signal throughout a clock distribution network. The propagation delay is computed using a round-trip packet. When a previous clock signal is received, a timer is set to a local clock's estimate of when the next clock signal will occur minus the propagation delay to the downstream device. When this timer expires, the clock signal is sent to the downstream device, which will allow it to arrive at the downstream device at the same time as the next clock signal is received on the local device.

Method and apparatus for accounting for propogation delay with distributing a clock signal

A clock selection circuit allows seamless switching between different clock signals in a clock distribution network. The clock selection circuit can be an Integrated Circuit (IC). The clock signals can be analyzed by a processor in communication with the IC to ensure the clock signals are validated. Analysis can include comparing time stamps between received pulses of the clock signals to determine if the clock signals are occurring at regular intervals. The processor can then assign a priority order to the clock signals and select one of the clock signals to use. An identifier associated with the selected clock signal can be programmed into the IC. The IC can then redistribute the selected clock signal to multiple other ICs in a hierarchical clock distribution network. Ultimately, the distributed clock signal can be received by server computers to ensure instances being executed have accurate and synchronized timing.

Clock selection in a clock distribution network

Systems and methods are provided for highly accurate synchronization of machine instances in a distributed, hosted computing environment to a reference timekeeper. In addition to a general communication network accessible to machine instances, the distributed environment includes a second network dedicated to carrying time information, such as a pulse-per-second (PPS) signal to isolated timing hardware within host computing devices. The isolated timing hardware can use the PPS signal, along with a reference time, to set a hardware clock. The isolated timing hardware can further provide an interface to machine instances that enables the instances to read the time of the hardware clock. This configuration enables many instances can share access to a single reference timekeeper, thus synchronizing those instances to a much higher accuracy than in traditional network-based time protocols.

Virtualized hardware clocks for providing highly accurate time information in hosted machine instances

A cage assembly may define a part of a computing appliance. The assembly can include a cage formed by walls and defining a continuous interior volume bounded by a top face, a bottom face, a right face, a left face, a front face, and a rear face. A first edge connector may be within a leftward portion of the interior volume. A second edge connector may be within a rightward portion of the interior volume and positioned laterally from the first edge connector. The arrangement may permit engagement with multiple individual-width plugs (e.g., each bearing an individual paddle card) or a single plug (e.g., bearing multiple paddle cards spaced laterally from one another and aligned for engagement with the first and second edge connectors within the cage).

Multiple-width plug arrangement for networking connectivity

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Santa Cruz, CA, United States of America

James Paul Rivers