International Business Machines Corporation

Texas Instruments Corporation

Globalfoundries Inc.

James Paul Di Sarro

Robert J Gauthier, Jr

JunJun Li

Souvick Mitra

Tom C Lee

Christopher Stephen Putnam

Nathan D Jack

Aravind Chennimalai Appaswamy

Farzan Farbiz

Shunhua Thomas Chang

Theodorus E Standaert

Chengwen Pei

Krishna Praveen Mysore Rajagopal

Kirk David Peterson

Vladislav Vashchenko

Akram Ali Salman

Michel J Abou-Khalil

Ann Margaret Concannon

Andrew A Turner

Nathaniel R Chadwick

Muhammad Yusuf Ali

Rajkumar Sankaralingam

Mariano Dissegna

Jun Jun Li

Robert J Gauthier

Lihui Wang

Yang Yang

Karmel Kranthi Nagothu

A lateral semiconductor controlled rectifier (SCR) includes a pwell and an nwell A plurality of p+ contact regions connect to the pwell and are spaced apart from one another by a dielectric material along a width of the pwell. There are a plurality of n+ contact regions connect to the nwell and are spaced apart from one another by dielectric material along a width of the nwell.

SCR having selective well contacts

An electrostatic discharge (ESD) device with fast response to high transient currents. The ESD device includes a short-pulse discharge (SPD) path and a long-pulse discharge (LPD) path. The SPD path provides robust response to ESD events, and it triggers a self-bias configuration of the LPD path. Advantageously, the SPD path reduces the risk of ESD voltage overshoot by promptly discharging short-pulse currents, such as a charge device model (CDM) current, whereas the LPD path provides efficient discharge of long-pulse currents, such as a human body model (HBM) current. In one implementation, for example, the SPD path includes a MOS transistor, and the LPD includes a bipolar transistor having a base coupled to the source of the MOS transistor.

ESD device with fast response and high transient current

An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.

Conductivity modulated drain extended MOSFET

Disclosed examples include an electrostatic discharge protection circuit including a shunt transistor coupled between first and second power supply nodes, a sensing circuit to deliver a control voltage signal to turn on the shunt transistor in response to a detected change in a voltage of the first power supply node resulting from an ESD stress event, and a charge pump circuit to boost the control voltage signal in response to the control voltage signal turning the shunt transistor on.

ESD protection charge pump active clamp for low-leakage applications

A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.

ESD network comprising variable impedance discharge path

An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers

A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.

Integrated circuit protection during high-current ESD testing

In some examples, an electrostatic discharge (ESD) device comprises an insulated-gate bipolar transistor (IGBT) comprising a source terminal, an anode terminal, a gate terminal, and a body terminal; and at least one reverse bias device comprising a first terminal and a second terminal, wherein the first terminal couples to the source terminal and the second terminal couples to the body terminal.

IGBT coupled to a reverse bias device in series

Growing community of inventors

Essex Junction, VT, United States of America

James Paul Di Sarro