International Business Machines Corporation

James Patrick Wood

Roy Rongqing Yu

Arthur Gilman Merryman

William Harrington Brearley

Kimberley A Kelly

Bouwe W Leenstra

Laertis Economikos

Eric D Perfecto

Chandrika Prasad

Paul F Findeis

Gregory S Boettcher

Thomas Anthony Wassick

Michael E Scaman

Charles J Hendricks

Ashwani K Malhotra

Richard Philip Surprenant

Kamalesh S Desai

Peter A Franklin

Robert Paul Katz

Stephen J Tirch, Iii

Patrick Michael O'Leary

Thomas Michael Biruk

An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.

Apparatus and method for use in manufacturing semiconductor devices

A multilayer thin film structure (MLTF) is provided having no extraneous via-pad connection strap plated metallurgy for defective vias needing removal. The method for making or repairing the MLTF comprises determining interconnection defects in the MLTF at a thin film layer adjacent to the top metal layer of the structure, applying a top surface dielectric layer and forming vias in the layer, applying a metal conducting layer and removing the metal conducting layer for via-pad connection straps of defective vias and at the intersection of XY lines used in the repair, defining the top surface metallization including a series of orthogonal X conductor repair lines and Y conductor repair lines using a photoresist and lithography and then using a phototool to selectively expose the photoresist to define top surface strap connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization using additive or subtractive metallization techniques.

Seed metal delete process for thin film repair solutions using direct UV laser

A semiconductor arrangement having a first active region and a dummy region on a surface of a substrate. The first active region and the dummy region are spaced from one another without any contact, and the dummy region is closer to an edge of the surface of the substrate in comparison to the first active region. Formed on the dummy region, first active region, and a portion of the substrate surface is a dielectric layer. The surface of the dielectric layer has an inactive portion and an active portion. A mask is disposed on the dielectric layer such that the mask contacts the inactive portion and does not contact the active portion.

Semiconductor arrangement preventing damage during contact processing

An apparatus for use in manufacturing a semiconductor device having input-output (IO) lands arranged in an IO array on an IO face includes a body having a plurality of cavities extending from an operating face into the body; the cavities are arranged in a cavity loci array which is in registeration with the IO lands when the apparatus is in a manufacturing position with the operating face generally adjacent the IO face. Each cavity has a depth and a lateral expanse which cooperate to establish a volume defined by a cavity bottom and at least one cavity wall. The volume accommodates an appropriate amount of solder material to establish a measure of the solder material on a facing IO land when the apparatus is in the manufacturing position. The depth is appropriate to facilitate wettingly attracting the solder material to the facing IO land when the apparatus is in the manufacturing position and the semiconductor device and the apparatus are exposed to appropriate ambient conditions to effect reflow of the solder material. The invention also includes a method for using the apparatus in manufacturing a semiconductor device.

Apparatus for providing solder interconnections to semiconductor and

A method for forming a ball grid array to provide a chip carrier with I/O capabilities is described. The method includes combining three distinct steps into one: partitioning a solder sheet into identical solder pieces using a mask provided with openings that match the footprint of the chip carrier; reflowing the solder pieces into solder balls; and joining the balls to the I/O pads of the chip carrier. By combining these three steps into one, a high throughput, high volume, defect free and contamination free operation for forming I/O connections thus results.

Ball grid array by partitioned lamination process

Multi-chip modules provided with a pin array may, under close scrutiny, display certain defects that may cause reliability problems. The presence of even one such defect necessitates the scrapping of the module. A method of salvaging the module is described, wherein the module is reworked by the method comprising the steps of applying a shearing force against the pins. During which the module is exposed to a temperature at or above that which is necessary for softening the braze material to remove the pins; polishing the surface of the module including the pads; evaporating the new pads; and attaching new pins to the pads.

Bottom-surface-metallurgy rework process in ceramic modules

Defects and latent defects are detected in connection patterns on a substrate by automated optical testing using bright field illumination and feature extraction template yielding an improved degree of feature discrimination. The feature extraction templates include angularly disposed vectors requiring detection of a predetermined (e.g. foreground) image value with a predetermined distance and a vector angularly interposed between those vectors which requires no detection of the predetermined image value within a distance which is greater than the predetermined distance. Thus, for successful detection of a defect, a portion of one of a set of templates having such a vector condition configuration must be wedged between areas of an image of a surface having the predetermined image values. This technique is implemented on commercially available automated optical inspection tools and results in avoidance of false detections even in the presence of a high density of image artifacts caused by the topologically sensitive bright field illumination employed.

Thin-film latent open optical detection with template-based feature

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Beacon, NY, United States of America

James Patrick Wood