International Business Machines Corporation

James Patrick Libous

Roger Paul Gregor

Joseph Natonio

Charles S Chiu

Joseph Maryan Milewski

Gulsun Yasar

Robert A Proctor

Robert A Gottschall

Rory D Loughran

A chip package comprises a substrate with a composite capacitor/stiffener on the substrate. In one embodiment of the present invention, the substrate comprises a plurality of dielectric layers and a plurality of metallic layers interlaced with the dielectric layers. One of the metallic layers is on a surface of the substrate. Another dielectric layer is adhered onto the one metallic layer. A metallic plate is adhered onto the other dielectric layer, opposite the one metallic layer. The metallic plate is electrically connected to power or ground. The one metallic layer is electrically connected to ground or power, respectively, such that the metallic plate, the other dielectric layer and the one metallic layer form a capacitor. The one metallic layer is joined to a respective one of the plurality of dielectric layers in a same manner as another of the plurality of metallic layers is joined to another, respective one of the plurality of dielectric layers. Other embodiments of the composite capacitor/stiffener are also disclosed.

Composite capacitor and stiffener for chip carrier

A method of analyzing I/O cell layouts for integrated circuits, such as ASICs, includes defining a proposed I/O cell layout on a selected chip image, providing a set of limit rules for electromigration, IR voltage drop and di/dt noise for the selected chip image, providing characteristics for each I/O cell type used in the proposed I/O cell layout, checking the proposed I/O cell layout by applying the limit rules to the proposed I/O cell layout and reporting all I/O cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image.

Fast method of I/O circuit placement and electrical rule checking

Power layers of a multi-layer connection structure forming a power distribution network are partitioned to accommodate all necessary voltages for one or more chips connected thereto in each power layer. By doing so, and rearranging vias as permitted by such partitioning via length is reduced while via numbers can be increased to reduce self-inductance of the structure. Transmission lines formed by conductors in the signal layers are referenced to the correct power supply and return/image currents are made of similar path length and substantially symmetrical for both positive- and negative-going signal transitions. These effects reduce delta-I noise to levels which preserve good signal-to-noise ratios to current and foreseeable reduced signal levels.

Multiple power distribution for delta-I noise reduction

A connection array for a chip provides a substantial increase in numbers of signal connection locations and a power distribution arrangement of improved robustness and noise immunity while accommodating multiple power supply voltages by providing pairs of sub-arrays aligned with chip edges and signal connection locations formed in columns orthogonal to a chip edge or segment of the chip perimeter. Signal connections in a column are spaced at a first pitch and columns of signal connections are spaced at a second pitch. Power connections corresponding to different power supply voltages are provided between columns of signal connections and along rows which are centered between rows of signal connections generally parallel to an edge of a chip. Power distribution layers may be formed as a mesh which extends in under the chip in alignment with power connections to the chip and beyond the perimeter of the chip, as well to provide multiple low-impedance power delivery paths to improve noise immunity. The connection pattern allows fewer layers of redistribution wiring to be used to escape the chip, reducing overall product cost. Thus improvements in functionality and performance can be supported at reduced cost, particularly for custom designed application specific integrated circuits.

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Endwell, NY, United States of America

James Patrick Libous