Asml Netherlands B.v.

Onetta, Inc.

James Patrick Koonmen

Jun Ye

Yu Long Cao

Arie Jeffrey Den Boef

Johannes Catharinus Hubertus Mulkens

Neal Patrick Callan

Wenjin Shao

Christophe David Fouquet

Bernardo Kastrup

James Benedict Kavanagh

Ronaldus Johannes Gijsbertus Goossens

Stefan Hunsche

Paul Francis Wysocki

Chia-Chi Wang

Ronaldus Johannes Gljsbertus Goossens

James W Sulhoff

A defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method including: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.

Computational wafer inspection

A computer-implemented defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method including: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.

Systems and methods for tuning photolithographic processes are described. A model of a target scanner is maintained defining sensitivity of the target scanner with reference to a set of tunable parameters. A differential model represents deviations of the target scanner from the reference. The target scanner may be tuned based on the settings of the reference scanner and the differential model. Performance of a family of related scanners may be characterized relative to the performance of a reference scanner. Differential models may include information such as parametric offsets and other differences that may be used to simulate the difference in imaging behavior.

Model-based scanner tuning systems and methods

Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.

Model-based process simulation systems and methods

The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.

Computational process control

Disclosed herein is a computer-implemented defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method comprising: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.

The present invention relates to a method for simulating aspects of a lithographic process. According to certain aspects, the present invention uses transmission cross coefficients to represent the scanner data and models. According to other aspects, the present invention enables sensitive data regarding various scanner subsystems to be hidden from third party view, while providing data and models useful for accurate lithographic simulation.

Scanner model representation with transmission cross coefficients

Disclosed herein is a computer-implemented defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method comprising: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; and determining or predicting, using the actual value, an existence, a probability of existence, a characteristic, or a combination selected therefrom, of a defect produced from the hot spot with the device manufacturing process.

Optical amplifiers and methods for manufacturing optical amplifiers are provided that allow amplifiers to be fabricated to match design expectations. Optical amplifiers may be manufactured by assembling passive optical components in the amplifier before assembling active optical components such as doped fiber coils. Passive losses may then be characterized and used to calculate the lengths of the fibers that should be used in the amplifier gain stages. Following corrections to the nominal doped-fiber lengths based on the measured passive losses, the passive and active components of the amplifier may be assembled and characterized. Final corrections may be made to the amplifier assembly based on these characterizations. For example, the lengths of one or more of the doped fibers may be adjusted. If desired, such length adjustments may be made to fiber coils in the mid-stage portion of the amplifier, so that the impact on the operating characteristics of the amplifier are minimized.

Growing community of inventors

Santa Clara, CA, United States of America

James Patrick Koonmen