International Business Machines Corporation

James Patrick Eckhardt

Paul David Muench

Scot H Rider

George E Smith, Iii

Shiu Chung Ho

Chandramouli Visweswariah

Eric A Foreman

Peter Anton Habitz

Keith Aelwyn Jenkins

Wiren Dale Becker

Howard Hao Chen

Nathan C Buck

Susan K Lichtensteiger

Tad Jeffrey Wilder

Timothy Gerard McNamara

Byron Lee Krauter

James Charles Gregerson

Alamgir A Tamboli

Controlling a PLL includes providing a voltage controlled oscillator (VCO) and coupling an output of the VCO to a shifter circuit. The shifter circuit has a shifter circuit output, the shifter circuit also including an activation input for receiving an activation signal, the shifter circuit causing at least one pulse of the output signal to be suppressed at the shifter output upon receipt of the activation signal. Controlling also includes coupling the shifter circuit output to a first frequency divider.

Multi-output PLL output shift

Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.

Chip design and fabrication method optimized for profit

A jitter measurement circuit and method having an input for receiving a reference signal whose jitter is to be measured, an input for receiving a clock signal having a series of cycles, and a measurement circuit for measuring the delay between the reference signal and the clock signal on a cycle by cycle bases, giving a cycle to cycle jitter measurement. The measurement circuit includes a plurality of n stages, each stage having a delay element including an input. The second and later delay elements have their inputs connected to the output of the previous stage and the first delay element has an input for receiving the reference signal. One of n latches is connected to the input of a corresponding one of the delay elements. Each latch has a clock input for receiving the clock signal, and an output for latching the value on the latches input when the clock input is clocked by an edge of the clock signal. An analysis logic circuit is provided having a plurality of n inputs connected to the outputs of the latches. The analysis logic circuit analyzes the values on the latches to give a measure of jitter.

Phase lock loop jitter measurement

A test circuit within an existing design to enable the test circuit to test directly within the circuit. This invention provides a way to test and measure the leakage of the PLL loop filter capacitor leakage during test with a simple digital tester using existing pins. The test PLL circuit has circuit a plurality of capacitors and responsive amplifiers circuits for measuring leakage including a first capacitor set having multiple transistors coupled in series and with a reference resistor circuit coupled to a first amplifier and a second capacitor set having multiple transistors coupled in series and said reference resistor circuit coupled to a second amplifier to measure the leaking across the respective capacitors coupled to said first and second amplifiers and to provide an output of the leakage for measurement with the output of said first and second amplifiers. The reference resistor circuit is broken into several series resistors and additional transistors and resistors are supplied with their terminals shorted out, to allow for RIT-B circuit tuning. The output of the test circuit provides the measurement of analog leakage to a digital tester for testing of chips having the circuit during manufacturing test.

PLL loop filter capacitor test circuit and method for on chip testing of analog leakage of a circuit

A duty cycle correction circuit is configured to adjust the duty cycle of a clock signal in a clock distribution network. The duty cycle correction circuit adjusts the duty cycle of the clock signal by adjusting the transitional delay in a single edge of each clock pulse of the clock signal without interrupting the other edge of each clock pulse of the clock signal. This feature enables the duty cycle correction circuit to adjust the duty cycle of the clock signal without interrupting the operation of a phase-locked loop (PLL) used in the clock distribution network. The duty cycle correction circuit includes a delay-control circuit coupled to a clock-inverter circuit. The delay-control circuit generates a delay-control voltage, which is provided to the clock-inverter circuit to control the transitional delay in a single edge of each clock pulse of the clock signal.

Single-edge clock adjustment circuits for PLL-compatible, dynamic duty-cycle correction circuits

An exemplary embodiment of the invention is a method for evaluating jitter of a phase locked loop circuit generating a phase locked loop output signal. The method includes generating a test initiate signal and generating a trigger signal in response to the test initiate signal. The trigger signal is synchronized with the phase locked loop output signal. A disturbance signal is generated to induce jitter in the phase locked loop output signal. The jitter in the phase locked loop output signal is then evaluated.

Method and apparatus for determining phase locked loop jitter

A tunable constant current source having temperature and power supply compensation is provided. The tunable constant current source includes a voltage regulator, a differential amplifier, a current source and a compensating load. The voltage regulator provides a substantially constant bias voltage V,. The differential amplifier receives the bias voltage V,and maintains a load voltage V,substantially equal to the bias voltage V,by way of a negative feedback. The current source generates a substantially constant current IREF from the differential amplifier. The compensating load varies with temperature changes to maintain the current IREF substantially constant, whereby the tunable constant current source may operate in a supply voltage range between about 0.5 volts to about 1.8 volts.

Tunable constant current source with temperature and power supply compensation

A reduction of multichip module computer system cycle time is achieved by using a voltage regulator for power supply noise attenuation to reduce jitter. The circuit for doing this includes an active filter network circuit for use in the multichip module of a computer system which generates a quiet analog VDD coupled directly to ground by using the low impedance power supply distributions which already exist in the module. The active filter network permits taking the power supply voltage from the module and stepping it down to a voltage needed by a phased lock loop via an active filter, said active filter comprising an op-amplifier and a source follower and a large value on module capacitor for a resistor network. The capacitor and resistor network acts as a filter with a large time constant where noise appearing on VDD,MOD is completely attenuated by this high value capacitor and resistor network part of our active filter network.

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Pleasant Valley, NY, United States of America

James Patrick Eckhardt