Lsi Logic Corporation

Ncr Corporation

Hyundai Electronics America, Inc.

At&t Global Information Solutions Company

Symbios Logic Inc.

Symbios, Inc.

James P Yakura

Richard K Cole

Derryl D Allman

Matthew S Von Thun

John W Gregory

John J Seliskar

Dim Lee Kwong

Crystal J Hass

Derryl D J Allman

Carl M Stanchak

Raymond A Turi

Steven L Haehn

Brad S Tollerud

Scott J Rittenhouse

A test transistor structure formed in a semiconductor device has a thick-oxide transistor with an elongated serpentine-shaped metal gate. The gate is used to first measure the threshold voltage of the thick-oxide test structure. Then, a current is passed through the elongated metal line which forms the serpentine gate to heat the area of the test structure. While being heated, a stress voltage is applied between the substrate and one end of the gate electrode, this stress voltage being much larger than the logic voltage used in operating thin-oxide transistors on the chip. After a selected time, the current is removed, the stress voltage is removed, and the threshold voltage of the thick-oxide transistor is again measured and compared to the original value. Any reduction in threshold voltage can be attributed to the migration of positive charge to the silicon-to-oxide interface beneath the gate, and is proportional to the area between the source and drain regions of the test transistor.

Mobile ionic contamination detection in manufacture of semiconductor devices

The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region which remains of the dielectric layer and between a peripheral region which remains of the dielectric layer.

Integrated circuit device and method of making the same using chemical mechanical polishing to remove material in two layers following masking

An electrical interconnection structure on an integrated circuit is provided that has a) a substrate layer; b) a diffusion barrier on the substrate layer; c) a copper layer on the diffusion barrier; and d) a copper oxide layer on the copper layer. Methods of making such an interconnection structure is also provided. Such an interconnection structure may be used as a rectifier to prevent damage of sensitive devices from voltage spikes.

Non-linear circuit elements on integrated circuits

An improved wafer scale integrated circuit is described which includes non-contact power and data transmission coupling. Wireless power and data coupling reduces the mechanical stresses and strains on the wafer, and makes better use of the wafer area. An additional benefit comes from allowing better heat transfer management. In one embodiment, power is provided by inductive coupling. Data flow into and out of the wafer is accomplished optically, using optical detectors to receive and light emitting diodes to transmit. Multiple devices are integrated onto the semiconductor wafer. Systems may be incorporated using the traditional die sites. Connections between systems are made in the space between die sites.

Method and apparatus for a wafer level system

The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region which remains of the dielectric layer and between a peripheral region which remains of the dielectric layer.

Integrated circuit device having a capacitor with the dielectric

A method of screening EEPROMs for data retention quality employs a UV source which is arranged to be impinged upon the devices while in wafer form, at or near an electrical probe station. Known data is stored in memory cells on an EEPROM chip while the chip is in wafer form, at a probe station. The wafer is then moved beneath a UV silo near the probe station and exposed to UV light, for a period of time and at an intensity which is sufficient to cause leakage of charge from potentially leaky floating gates. The wafer is again subjected to electrical probe where the amount of change in retained charge is detected. From this test, an indication of the charge retention ability of the devices is obtained. The UV light increases the energy state of the stored charge thus accelerating the decay of the stored charge located on the floating gates in the EEPROM device. Bits that have inherent leakage paths decay more rapidly.

Testing semiconductor devices for data retention

The present invention provides an integrated circuit chip having one or more circuit elements that perform a desired circuit function with the circuit elements being encompassed by a molding compound that forms a package for the chip. The molding compound has a capacitance associated with it. The integrated circuit chip includes a second integrated circuit element within the molding compound in which the second integrated circuit element monitors the molding compound to detect a change in capacitance in the molding compound resulting from a removal of a portion or all of the molding compound. In response to a detection of a change in capacitance, the second integrated circuit element alters the desired circuit function provided by the other integrated circuit elements.

Method and apparatus for protecting functions imbedded within an

A method and structure for sensing data such as temperature with respect to objects such as silicon wafers undergoing fabrication or other processes involve the use of a monitor element of material and configuration similar to that of the objects being processed. A structure such as a closed loop or segment of a spiral may be formed on the surface of the monitor element, and acts as a secondary coil when brought into operative relation with a transformer structure which includes a primary coil, a current source and a sensing device. The sensing device senses variations in the electrical characteristics in the primary coil, caused by the presence of the monitor element, and can thereby determine the temperature or other desired data relating to the monitor element, which is substantially the same as comparable data for the objects being processed.

Method for manufacturing a monitor element

Structure and method for remotely measuring process data

A memory security device within a chip which employs a power source coupled to the memory. The power source produces a signal having a level sufficient to erase or destroy the memory when the chip is exposed to acid. The power source includes an electrolytic cell for producing a direct voltage output, and an electrolytic signal amplification circuit coupled between the electrolytic cell and the memory.

Memory security device

A nonvolatile memory device comprising first and second transistors connected between respective first and second terminals and a reference potential terminal, the transistors having first and second floating gates, respectively, for storing complementary charges. The device further comprises first and second input lines capacitively coupled to the gates, and means for providing a biasing voltage slightly in excess of the threshold voltage of the transistors to the input lines.

Growing community of inventors

Colorado Springs, CO, United States of America

James P Yakura