Amdahl Corporation

James P Millar

Jeffrey A Thomas

Theodore S Robinson

Ajay K Shah

Robert A Ertl

Eddie B Collins

Gary A Woffinden

Mark Semmelmeyer

Joseph A Petolino

Christopher D Finan

Ronald D Weber

Shen H Wang

Clifford A Petersen

The invention provides a method and apparatus for immediate control communications between supervising and main processor units. A method in accordance with the invention comprises the steps of: providing a communications memory means within a first clocked system (main system); providing a protocol means within the first clocked system (main system) for indicating various communications states; providing a scan interface, operatively coupled to the communications memory means and the protocol means, for interrogating the state of the protocol means and for scanning data into or out of the communications memory means within a first clocked system (main system); coupling an external second system (SVP) by way of the scan interface to the protocol means and the communications memory means; operating the protocol means so as to indicate to the external second system (SVP) when it is permissible for the second system (SVP) to scan data into or out of the communications memory means; and further operating the protocol means so as to indicate to the first clocked system (main system) whether and/or when the external second system (SVP) has scanned data into or out of the communications memory means.

System having main unit for shutting off clocks to memory upon

Determinism is maintained in a synchronous first system although the first system receives behaviorchanging signals from a second system running asynchronously relative to the first system. The second system refrains from sending behavior-changing signals to the first system until the first system stops its clock at a prespecified clock cycle and signals the second system of the event. The second system then downloads the behavior-changing signals into the first system and restarts the first system clock. The first system awakens to discover that the behavior-changing signals have been received during the prespecified clock cycle. This is repeated over multiple runs, and in each run the same behavior-changing signals are transferred at the same prespecified clock cycles of the first system. Deterministic behavior is thereby maintained in the first system.

Method and apparatus for maintaining deterministic behavior in a first

The computer system architecture utilizes the ability to actively force a ghost line state in management of a split instruction and operand cache associated with an instruction unit with respect to a secondary system integrity cache tag store separately managed by a system controller. The split instruction and operand cache and the system controller tag store permit the management of multiple copies (line-pairs) of a memory line by storing address tag line pair state information with respect to each memory line present in the split-cache to allow determinations of whether and where the respective memory line pair members reside upon access of any one member. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depending on whether the operand buffer destination is a memory line that is a member of a line pair. A ghost line state is forced whenever a modified memory line, existing as a member of a line pair is to be stored into the operand cache and a concurrent storage of the modified memory line in the instruction cache cannot be performed.

Microprocessor system private split cache tag stores with the system tag

A computer system architecture implementing multiple central processing units, each including a split instruction and operand cache, and that provides for the management of multiple copies (line pairs) of a memory line through the use of a line pair state is described. Systematic management of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture implements the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the instruction and operand cache buffers of a single central processor. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depending on whether the operand buffer destination is a memory line that is a member of a line pair.

Computer system architecture implementing split instruction and operand

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Santa Clara, CA, United States of America

James P Millar