Quantum Corporation

James P McGrath

Hung C Nguyen

John Welsford Brooks

Bruce R Peterson

James A Henson

Tim R Glassburn

James H Do

Michael L Raab

Jeffrey Herbert Appelbaum

A synchronous DMA burst transfer method is provided for transferring data between a host device and a peripheral drive device connected by an ATA bus. The method provides synchronous data transfer capability in an asynchronous system by having one device in charge of both a strobe signal and a data signal. When a host read or write command is delivered to the peripheral drive device, the peripheral device decides when to start the synchronous DMA burst. For a read command, the peripheral device requests the synchronous DMA burst then drives a data word onto the ATA bus after the host acknowledges that it is ready to begin the burst. After allowing time for the data signal to settle, the peripheral device toggles a strobe signal from a high state to a low state. The host sees the edge of the strobe signal at which time the host latches the data word on the bus. Additional data words can be driven on the bus and the strobe signal can be retoggled to latch the additional data words into the host. After all data words have been transferred, the strobe signal is returned to a high state so that it is ready to be used for another host command. By having the device which is sending the data in charge of both the strobe signal and the data signal, the method reduces timing delays and provides a data transfer rate up to 33 MBytes/sec. The method is easily implemented in existing systems and is backward compatible with existing transfer protocols.

Synchronous DMA burst transfer protocol having the peripheral device

An improved disk drive architecture includes a microcontroller interface circuit connected between a drive microcontroller and a buffer controller. The microcontroller interface circuit includes address mapping registers for mapping at least one predetermined portion of directly addressable memory of the microcontroller to address locations of the drive's cache buffer. The buffer controller circuit includes an access arbitration circuit for arbitrating requests for access to the cache buffer by the drive's data sequencer, the drive's host interface controller and the drive's microcontroller. A microcontroller wait state generator responds to the access arbitration circuit by generating and applying a wait state sequence to the microcontroller until a request it makes for access to the cache buffer can be executed.

Shared memory array for data block and control program storage in disk

Growing community of inventors

Mountain View, CA, United States of America

James P McGrath