Silicon Graphics, Incorporated

Other

James P Laudon

Daniel E Lenoski

John C Manton

Ryan Christopher Jones

Michael E Anderson

An inner collar is co-axially aligned with a longitudinal axis of an outer collar. The outer and inner collars are and separated by a gap. A plurality of ribs disposed within the gap and interconnect the inner collar to the outer collar. The inner collar defining an interior passage. A channel disposed within the outer collar and the inner collar. The channel extending along the longitudinal axis and opening at one side into the passage and opening at an opposite side exteriorly of the outer collar. The outer collar, inner collar, and plurality of ribs are constructed of a resiliently deformable material thereby allowing the outer and inner collars to resiliently deform for removably receiving a tubular container grip and allowing the outer collar and the plurality of ribs to resiliently deform for increasing gripping capabilities of a human hand.

Auxiliary gripping member

A bucket has a generally cylindrical configuration with an open top, a closed bottom, and a side wall extending there between. The bucket has an axis. The side wall has a first major section extending between the open top and the closed bottom. The side wall has a second major section extending between the open top and the closed bottom. The first and second major sections are separated to circumferentially create a first opening and a second opening. The first and second major sections are spaced from the axis by primary distances. The side wall has a first minor section and a second minor section. The first and second minor sections are located adjacent to the first and second openings respectively. The first and second minor sections are spaced from the axis by secondary distances greater than the primary distances.

Wide-body roller paint system

A multiprocessor computer system and method for maintaining coherency between virtual-to-physical memory translations of multiple requestors in the system. A poison bit is associated with a memory block in the system. The poison bit is set to indicate that a virtual-to-physical memory translation for the memory block is stale. An exception is generated in response to an access by one of the requestors to the memory block if the poison bit is set, thereby indicating to the requestor that the virtual-to-physical memory translation entry for the memory block is stale. The virtual-to-physical memory translation for the memory block is then updated with a virtual memory translation corresponding to a new physical location for the memory block. In an embodiment having a cache-based multiprocessor system, the method further comprises the step of invalidating all cached copies of the memory block. In this case, the invalidating step and the setting step must be performed as an atomic operation.

System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer

A high memory capacity dual in-line memory module (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system including a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.

High memory capacity DIMM with data and state memory

A system and method for partitioning to support high availability of a multiprocessor system. The system comprises a plurality of masters, including processors, input/output devices, or the like, and is divided into regions. Per-region access rights are assigned to the system resources. The regions are grouped into partitions, wherein a partition is a portion of the system that is treated as a single unit with respect to failure. Failure of a master in a given region only affects resources accessible to that given region. Per-region access can be to main memory on a per-page basis, for example. Alternatively, the per-region access can limit access to directory storage, input/output ports and devices, control or diagnostics registers.

System and method for multiprocessor partitioning to support high

A high memory capacity dual in-line memory modules (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.

High-memory capacity DIMM with data and state memory

System and method for maintaining coherency of virtual-to-physical

A page migration controller is described. The page migration controller determines whether a memory page addressed by a memory access request should be migrated from a local processing node to a requester processing node. The page migration controller accesses an array to obtain a first count associated with the addressed memory page and the requester processing node, and a second count associated with the addressed memory page and the local processing node. The first count is incremented, and then the second count is subtracted from the incremented first count to obtain a difference between the second count and the incremented first count. A comparator determines whether the difference is greater than a migration threshold value. If the difference is greater than the migration threshold value, then a migration interrupt is issued.

Apparatus and method for page migration in a non-uniform memory access

A high memory capacity DIMM for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM is configured for use in a DIMM pair. In the DIMM pair, a first DIMM includes a first data memory having first and second memory bank portions for storing data, and a first state memory configured to store state information corresponding to data stored in a first memory bank. A second DIMM includes a second data memory having third and fourth memory bank portions for storing data, and a second state memory configured to store state information corresponding to data stored in a second memory bank. The first memory bank is formed from the first memory bank portion and the third memory bank portion. The second memory bank is formed from the second memory bank portion and the fourth memory bank portion.

Dimm pair with data memory and state memory

A multiprocessor system having a plurality of requestors, a memory and memory directory controller employing directory-based coherence. The system implements a method to detect dropping of clean-exclusive data. Only one intervention message is permitted to target an exclusive object held by a first requestor, wherein the intervention message is caused by a second requestor. The system detects whether the first requestor has an outstanding writeback for the object targeted by the intervention message, as well as whether the first requestor has a clean-exclusive, dirty-exclusive or invalid copy of the object targeted by the intervention message. A clean-exclusive copy of the object has been dropped when no outstanding writeback is detected and the first requestor has the object in the invalid state.

Directory-based coherence protocol allowing efficient dropping of

A memory controller in a computer system is described. The memory controller maintains a directory comprising a plurality of entries. Each entry is associated with a memory block. The memory controller maintains an entry of the directory in a modified fine bit vector format when a memory block associated with the entry is cached in one or more nodes all of which are within a single partition of the computer system. The entry when maintained in the modified fine bit vector format comprises a partition field storing information identifying the single partition, and a modified fine bit vector field storing information identifying nodes in the single partition where the memory block is cached. The memory controller maintains the entry in a modified coarse bit vector format when the memory block is cached in multiple nodes distributed among P partitions of the computer system, where P is greater than one. The entry when maintained in the modified coarse bit vector format comprises Q partition fields each storing information identifying one of the P partitions, and Q modified coarse bit vector fields each storing information identifying nodes in one of the P partitions where the memory block is cached.

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Menlo Park, CA, United States of America

James P Laudon