International Business Machines Corporation

James P Kuruts

Adrian Stephen Butter

Chang Y Kao

Robert Walter Berry, Jr

Christopher J Kuruts

Sivarama K Kodukula

Michael Edward Criscolo

Steven Joseph Smolski

Michael Anthony Sorna

Leonard R Chieco

Christopher R Conley

Chang-Yung Kao

Brian S Finkel

A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.

Implementing a programmable DMA master with write inconsistency determination

A system and method for semiconductor identification chip read out is presented. A user uses a stand-alone handheld device to extract product data, which includes manufacturing process attributes, from a semiconductor device. The semiconductor device couples to the hand held device through a subset of pins, such as a power pin, a ground pin, a clock in pin, and a data out pin. When coupled, the handheld device provides a clock signal to the semiconductor device. In turn, on chip logic within the semiconductor device detects the clock signal and gathers internal product data. Once gathered, the on chip logic provides the product data to the hand held device through the data out pin for a user to view. As a result, the user may track semiconductor devices more efficiently.

System and method for semiconductor identification chip read out

System and method for implementing a programmable DMA master with data checking utilizing a drone system controller

A detector detects the end of a serial bit stream wherein the serial bit stream is based on one clock and the detector (and other associated circuitry) is based on a different, asynchronous clock. An Exclusive OR block receives the serial bit stream and a digital strobe signal according to IEEE High Performance Serial Bus Specification 1394. Based on this standard, one but not both of the serial bit stream and digital strobe signal changes level every data interval. The Exclusive OR block outputs a periodic signal when the serial bit stream and digital strobe signal are present but outputs a constant digital level upon termination of the serial bit stream and digital strobe signal. The detector also includes a first register coupled to receive the output of the receiver, a second register coupled to receive the output of the first register and a third register coupled to receive the output of the second register. All three registers are clocked simultaneously. The serial bit stream and digital strobe signal are asynchronous relative to the clock. Hardware logic determines when contents of the third register is same as contents of the second register; this indicates termination of the serial bit stream and digital strobe signal.

Apparatus and method for detecting end of serial bit stream

A device converts serial data based on one clock to parallel data based on a different, asynchronous clock. The data converter comprises one register bank including first and second registers and another register bank including third and fourth registers. A data input of the first register and a data input of the third register are coupled to receive the serial data. A data input of the second register is coupled to a data output of the first register. A data input of the fourth register is coupled to a data output of the third register. A first clock triggers the first and second registers simultaneously and a second clock triggers the third and fourth registers simultaneously. The first and second clocks alternate with each other. Fifth, sixth, seventh and eighth registers have respective data inputs coupled to respective data outputs of the first, second, third and fourth registers. A third clock triggers the fifth and sixth registers simultaneously to latch bits 0 and 2, respectively, of a series of four bits. A fourth clock triggers the seventh and eight registers simultaneously to latch bits 1 and 3, respectively, of the series of four bits.

High speed asynchronous serial to parallel data converter

A system and method for implementing a new protocol that uses new data structures in order to improve the performance of a token ring without changing its topology or degrading its fairness. A primary sender sends a data frame containing a data field addressed to a primary receiver. The protocol allows the primary receiver to enter 'transmit mode' and assume another role as a secondary sender when the data frame is received and copied. The secondary sender overwrites the data field. Then, the secondary sender designates a secondary receiver to receive the update data and sends an acknowledgement message back to the primary sender to indicate that it has received data. The secondary receiver sends an acknowledgement to the secondary sender when the secondary transmission data is received. The primary sender checks for an acknowledgement from the primary receiver when the data frame returns. Then the primary sender transmits the data frame downstream. The primary sender regenerates a token and either releases it or seizes it based on whether it has more data to send. The secondary sender verifies the acknowledgement from the secondary receiver and returns to 'listen mode'.

Method and system for improving the performance of a token ring network

A method and system for increasing performance on a standard dual ring token ring by generating one or more sub-tokens so that multiple data transmissions can occur concurrently. Upon receipt of a data frame from the token holder, interface logic enables a receiver to generate a sub-token frame. The sub-token is used to notify the next downstream station that it may transmit data frames to other downstream stations. In this way, a second data transmission path can be established between downstream stations. In a similar manner, the receiver of a data frame sent by a sub-token owner will generate a sub-token frame for use by the next downstream station when its data arrives. Each sub-token is used to create a new sub-ring, thus allowing for concurrent data transmissions. Each new sub-ring must obey token ring protocol to avoid data collisions.

Method and system for implementing sub-tokens on a token ring network

An improved DES unit internally checks whether the DES algorithm is being performed without error. A standard DES algorithm performs an initial permutation of input data and then multiple rounds or iterations of the following: expanding part of a result of the initial permutation for the first iteration and a result of the previous iteration for the subsequent iterations, exclusive ORing a result of the expansion with key bits, performing a selection function on a result of the exclusive ORing, permuting a result of the selection function, and exclusive ORing a result of the permuting. In the improved DES unit, data check bits that correspond to the input data which has been expanded are exclusive NORed with key check bits that correspond to the key, and a result of the exclusive NORing is checked against a result of the exclusive ORing to identify any errors in the operation of the basic DES unit. Also, a check selection function is performed on the result of the exclusive ORing. A result of the check selection function is exclusive NORed with data check bits for another part of the input data to yield input data for input to the expanding function for a next iteration. Also, the improved DES unit checks for accuracy in processing an input key by permuted choicing the input key, key shifting a result of the permuted choicing, and checking a result of the key shifting against key check bits which correspond to the input key and bypass the permuted choicing and key shifting functions.

DES encryption and decryption unit with error checking

A system translates a first group of cipher blocks based on a first encryption key to a second group of respective cipher blocks based on a second encryption key. Respective cipher blocks of the first and second groups represent the same data. The system comprises decryption hardware for sequentially decrypting the cipher blocks of the first group based on the first key. Encryption hardware is coupled to receive decrypted blocks output from the decryption hardware and sequentially encrypts the decrypted blocks into respective cipher blocks of the second group based on the second encryption key. A control unit controls the encryption hardware to encrypt the decrypted blocks into the respective cipher blocks of the second group while the decryption hardware decrypts cipher blocks of the first group. Consequently, decryption and encryption operations occur in parallel and the translation process is expedited.

System for translating encrypted data

ANSI X3.92 Data Encryption algorithm is public knowledge, and is widely used where data security and integrity is vital, such as commercial banks, secret service organizations etc. Even though this algorithm is feasible to implement in software, it is impractical to achieve desired performance for most of the applications. Hence, a hardware solution is highly recommended. Prior art DES hardware in CMOS technology served performance needs of low-end and mid-range systems only, due to the technology constraints. However, some of these constraints are removed through the technology breakthroughs and the current CMOS is well suited for high performance applications. While prior art DES designs allowed one round per cycle to minimize the cell count, the current technology allows of multiple rounds per cycle due to the denser CMOS chip technology. In order to maximize the number of rounds for a given cycle time, careful study of algorithm to determine the critical paths from a logic implementation perspective is required. This invention identifies one such path in f-function of the DES algorithm, where the expanded data and the key is XOR'd prior to entering S-function. It is mathematically proven that if the left half of the input data is expanded and XOR'ed with the second key at the same time the right half of the input data which is still going through its XOR, S-function, permute and expansion, then this expanded result can be immediately XOR'ed with the left input data being expanded and XOR'ed in parallel. The resulting output can be used as input to the next S-function, thus eliminating a stage of expansion and XOR logic for all subsequent S-function inputs in rounds 2 through 15.

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Forest City, PA, United States of America

James P Kuruts