Bell Telephone Laboratories

James Owen Dimmick

John Francis O'Neill

Theras Gordon Lewis

Lucian Philip Fabiano, Jr

Circuitry is disclosed for allocating requests for demand-shared bus access among a plurality of requesting ports. During bus contention time, each requesting unit synchronously and sequentially applies the digits of its unique priority code to the bus beginning with the most significant digit. Each requesting unit remains in contention only so long as each digit it applies is greater than or equal to the digit applied by any other unit. After the application of all digits, only the requesting unit having the highest code remains in contention and it seizes the bus. A polarity control conductor is provided, selectively altering the preference that is normally specified by the assigned priority codes. The application of a reversal signal to this conductor for a given interval of time causes each requesting unit to invert each bit of its priority code it applies to the bus during this time interval. The polarity conductor thus permits the normal preference between units to be altered selectively in any pattern that may be desired.

Circuitry for allocating access to a demand-shared bus

Processor circuitry is disclosed for setting a memory address register to a predetermined address upon the receipt of an interrupt request. The receipt of the request extends a steady state signal through an AND gate to the input of the counter to hardwire jam it to a predetermined address which defines the memory location of the first word of a subroutine associated with the request. The jam signal remains on the register input until the addressed memory location is read out. A readout of this location disables the AND gate and removes the jam signal from the counter. The AND gate is restored to normal when the last word of the subroutine is read out to permit new interrupt requests to be honored. The continuous application of the jam signal to the register until the addressed location is read out increases the probability of the register being successfully set to the correct address.

Interrupt control circuit

A processor is disclosed having improved circuitry for (1) generating m+n-bit address words from n-bit data words and (2) converting m+n-bit address words back into data words having an n-bit format. The processor includes a first arithmetic unit (AMU) that is n bits wide and which receives n-bit words from a data bus. The processor further includes a second AMU that is m bits wide and which is connected to receive the m least significant bits of an n-bit word stored in the first AMU. An m+n-bit address word is formed by (1) applying a first n-bit word from a system data bus to the first AMU with the m most significant bits of the address word to be formed being contained in the m least significant bit positions of the first word, (2) transferring the m least significant bits from the first AMU to the second AMU and concurrently applying from the data bus to the first AMU a second n-bit word representing the n least significant bits of the address word, and (3) concurrently reading out both AMUs to apply an m+n-bit address word to a system address bus. This procedure is reversed to convert an m+n-bit address word into n-bit data words.

Processor circuit

An electronic key telephone system is disclosed in which connections among the station sets and telephone lines are made in a central time division switching network remote from the station sets. Each station set and line is equipped with a port circuit having an individual shift register for defining the time slot interval during which a connection may take place. To assign a time slot to a port circuit, the main controller interrogates the network to find an idle time slot and then furnishes that time slot number to the network controller. In order to save central memory and to increase system reliability, the main activity memory which stores an indication of which ports are or should be interconnected in the network need not contain any reference to the time slot number assigned for the particular connection. In order periodically to verify that actual network connections reflect the state of the activity memory, two types of audits are performed. A fast audit accesses the activity memory to find an active port and then accesses the network to find the time slot assigned the port. If no time slot or more than one time slot are assigned, an error indication results. A slow audit is performed which steps through all idle port circuits and which clears network connections for ports whose activity memory indicates an idle state but for which a network time slot is found.

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Boulder, CO, United States of America

James Owen Dimmick