Agilent Technologies, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Other

Hewlett-packard Company

Airtech Gmbh

James Oliver Barnes

Charles E Moore

Alvin Leng Sun Loke

Robert Keith Barnes

Christopher Koerner

Benny W H Lai

Nurwati Suwendi Devnani

David J Leary

Alberto Gutierrez, Jr

Masaharu Goto

Mark A Wahl

James R Hulings

Ronald R Kennedy

Michael M Oshima

A phase-locked loop includes a voltage-controlled oscillator and a charge-pump loop filter. The voltage-controlled oscillator includes a varactor having a first set of capacitor cells configured to adjust a capacitance based on a first control voltage, and a second set of capacitor cells configured to adjust a capacitance based on a second control voltage. The charge-pump loop filter receives a first and a second update signal, each having at least one state based on a phase difference between a first clock and a second clock, and comprises a first component and a second component. The first component is configured to adjust, during an update period, a voltage across an impedance from a reference level based on the states of the first and second update signals and to return the voltage across the impedance to the reference level prior to an end of the update period, wherein the voltage across the impedance comprises the first control voltage. The second component is configured to adjust a voltage across a capacitor based on the states of the first and second input signals, wherein the voltage across the capacitor comprises the second control voltage.

Low-jitter charge-pump phase-locked loop

In one embodiment, the present invention provides a phase-locked loop comprising a charge-pump loop filter and a phase detector system. The charge-pump loop filter is configured to provide a control voltage having a voltage level based on a state of a first control signal and on a state of a second control signal. The phase detector system is configured to receive a first clock, a second clock, and a control signal defining a plurality of states including a first state and a second state. The phase detector system is further configured to provide the first control signal and the second control signal each having a state based on a phase difference between the first and second clocks when the control signal has the first state, and to provide the first control signal and second control signal each having a state asynchronously controlled by the control signal when the control signal has the second state.

Phase detector system with asynchronous output override

A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Integrated circuit package

A method and apparatus for processing a signal is presented. An accumulator receives an input signal and generates an accumulated value. A hysteresis controller sets an adjustable upper and lower limit. The upper and lower limits are compared with the accumulated value in a comparator. The comparator outputs a result, which is fed back into the hysteresis controller through a feedback loop. Once the input signal stays within the upper and lower limits, a test signal is considered within specification. When the input signal is outside of the boundary limits, a corrupt test signal is detected.

Limit detector with hysteresis

Integrated circuit and method of manufacturing an integrated circuit and package

The addition of an array of transistors through areas of the circuit where active devices normally don't exist, such as under routing channels. By connecting this array of transistors such that the gates are tied to one power supply and the sources and drains to another, the transistors act as bypass capacitors between the power supplies and act to reduce noise on the supplies. Also, the transistors may later be reconnected through changes in the design to form diodes, inverters, buffers, or other logic gates to allow changes to the circuit late in the design cycle.

Multi-purpose transistor array

A hip brace that dramatically reduces the pain and discomfort associate with hip degeneration. In one embodiment, the hip brace includes a girdle adapted to be wrapped around the user's waist, and a support member including an upper portion connected to the girdle and a lower portion adapted to provide lateral and upward support to the user's buttock. The lower portion is thicker (e.g., at least three times thicker) than said upper portion to facilitate support of the user's buttock. In order to provide additional support, the hip brace can further include a formed spring support connected to the support member. Preferably, the hip brace further includes at least two support straps connecting the lower portion with the girdle. In a preferred embodiment, the support member includes an inflatable member and an inflater connected to the inflatable member. For example, the inflatable member can include an inflatable bladder, and the inflater can include a hand pump, a conduit connecting the hand pump to the inflatable member, and a one-way valve.

Hip brace

A system for generating an analog regulating voltage to be supplied to one or more circuit elements on an integrated circuit. The circuit elements have operational characteristics that are voltage dependent and the analog regulating voltage having the a property of changing with temperature, power supply voltage, and manufacturing process variations so as to substantially eliminate the effects of such variations on the operational characteristics of the circuit elements.

System for generating an analog regulating voltage

The present invention is a time vernier providing fine timing control of an input signal having coarse timing edges. The time vernier comprises a receiving means for receiving a value representing a desired time delay to be added to the coarse timing edge input. The desired time delay may have both fine and coarse delay aspects. The time vernier also comprises a first decoding means for decoding the fine delay aspect and generating fine delay control signals, as well as a second decoding means for decoding a coarse delay aspect and generating coarse delay control signals. A delay line is also included in the time vernier which has inputs to receive the input signal having coarse timing edges, the fine and coarse delay control signals, and a control voltage which automatically adjusts with temperature and power supply variations, so as to provide for temperature and power supply compensation. The delay line combines the fine and coarse delay signals to provide an output signal with fine timing edges. Furthermore, the architecture of the present invention enables an automated method of calibration in order to adjust fine and coarse delay elements for fabrication process variations and photolithography variations.

CMOS pseudo-NMOS programmable capacitance time vernier and method of

A method for fabricating a solid state semiconductor gas sensor and the semiconductor sensor itself for use in equipment detecting small amounts of H.sub.2 S. The method of sensor fabrication comprises spray deposition of a mixture of metal oxides mixed together with various metal and non-metal materials which serve in the finished product as activators, dopants, and/or film binder materials, and including in suspension a molecular sieve material, for enhancing porosity on a scale of molecular dimensions in the finished sensor. All of the foregoing materials are suspended in a suitable solution and preferably sprayed onto a heated insulating substrate to form the finished product. The example sensor, capable of selective detection of H.sub.2 S in air and a sensitivity of less than 1 PPM (part per million), is comprised of a platinum activated alumina, tin oxide, and zeolite molecular sieve material.

Method for fabricating a semiconductor gas sensor

A semiconductor gas sensor for use in equipment for detecting small amounts of H.sub.2 S. The method of sensor fabrication comprises spray deposition of a mixture of metal oxides mixed together with various metal and non-metal materials which serve in the finished product as activators, dopants, and/or film binder materials, and including in suspension a molecular sieve material, for enhancing and defining porosity on a scale of molecular dimensions in the finished sensor. All of the foregoing materials are suspended in a suitable solution and preferably sprayed onto a heated insulating substrate to form the finished product. The example sensor, capable of selective detection of H.sub.2 S in air and a sensitivity of less than 1 PPM (part per million), is comprised of a platinum activated alumina, tin oxide, and zeolite molecular sieve material.

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Fort Collins, CO, United States of America

James Oliver Barnes