Blackberry Corporation

Paratek Microwave Incorporated

Research in Motion Corporation

James Oakes

James H Martin

Andrey Kozyrev

Alexandr Prudan

William E McKinzie, Iii

Matthew Russell Greene

Edward Horne

Guillaume Alexandre Blin

Greg Mendolia

Izz Khayo

Daniel Charles Boire

Edward Provo Wallis Horne

William Macropoulos

Edward Provo Horne

William E Mckinzie

A system that incorporates teachings of the present disclosure may include, for example, a first solid electrode, a second electrode separated into subsections, and a dielectric medium separating the subsections from the first solid electrode, where the subsections of the second electrode include a first group of subsections and a second group of subsections, where the first group of subsections are connectable with a first terminal for receiving an input signal, and where the second group of subsections is connectable with a second terminal for providing an output signal. Other embodiments are disclosed.

Thin films capacitors

A system that incorporates teachings of the subject disclosure may include, for example, a plurality of variable capacitors, a first set of resistors for applying a bias voltage to each variable capacitor of the plurality of capacitors, and a second set of resistors for providing a DC ground to each variable capacitor of the plurality of capacitors. The system can include one or more of multiple bias points, anti-parallel diodes, a choke inductor or a ground inductor. Other embodiments are disclosed.

Apparatus and method for high linearity tuning

Thin film capacitors

A system that incorporates teachings of the subject disclosure may include, for example, emulating a behavior of an RF capacitive device utilizing a mirror circuit; and providing feedback signals to an input of an operational amplifier via a feedback node coupled with the mirror circuit. Other embodiments are disclosed.

Method and apparatus for reducing charge and discharge time of capacitive elements

An embodiment of the present invention provides a method, comprising reducing the losses due to electro-mechanical coupling and improving Q in a multilayered capacitor by placing a first capacitor layer adjacent at least one additional capacitor layer and sharing a common electrode in between the two such that the acoustic vibration of the first layer is coupled to an anti-phase acoustic vibration of the at least one additional layer.

Capacitors adapted for acoustic resonance cancellation

An embodiment of a tunable capacitor can include a plurality of capacitors connected in series where at least two capacitors of the plurality of capacitors share a common electrode where the at least two capacitors are in lateral proximity and a bias that is capable of being applied to the at least two capacitors whereby the at least two capacitors vibrate in opposite phase to each other when the bias and an RF signal is applied to the at least two capacitors.

At least an embodiment of the present technology provides a capacitor, comprising a substrate, a first solid electrode disposed on the substrate, a second electrode broken into subsections, the subsections connected by a bus line and separated from the first electric by a dielectric medium. The second electrode broken into subsections may have a lower resistance than the first solid electrode and by changing the width and length of the sides of the subsections, the resistance of the first electrode is modifiable.

Optimized thin film capacitors

An embodiment of the present disclosure provides a method to reduce acoustic vibration in a multilayered capacitor stimulated by a radio frequency signal by placing a first capacitor layer adjacent to second capacitor layer sharing a common electrode such that the acoustic vibration is reduced by applying one or more anti-acoustic vibration bias voltages to the multilayered capacitor. Other embodiments are disclosed.

An embodiment of the present invention provides a device, comprising a multilayered tunable dielectric capacitor, wherein said multilayers of tunable dielectric are adapted to be DC biased to reduce the dielectric constant; and wherein the DC bias is arranged so that the number of layers of tunable dielectric biased positively is equal to the number of layers of tunable dielectric biased negatively.

An embodiment of the present invention provides an apparatus, comprising an integrated circuit, wherein a first portion of the integrated circuit is placed on a top tier substrate and a second portion of the integrated circuit is placed on a bottom tier substrate stacked adjacent the top tier substrate and wherein the first portion and the second portion of the integrated circuit are interconnected; and printed spiral arms stacked vertically on both the top and bottom surface of the top tier substrate thereby creating high Q inductors.

Growing community of inventors

Westford, MA, United States of America

James Oakes