Harris Corporation

Harris Data Communications, Inc.

James O Rozell

David W Abmayr

A selective memory addressing scheme employs a programmable read only memory (PROM) which responds to the opcode of the next instruction to be executed and supplies control information to memory module selection registers.The memory module selection registers operate in conjunction with the internal address registers to provide the necessary steering information for properly addressing the intended memory location. The PROM is programmed in accordance with the instruction set by which the processor operates and is coupled to decode the opcode contents of the instruction register that has been loaded, in a lookahead fashion, with the instruction following the instruction presently being executed by the central processing unit. The PROM has a first output that defines whether or not a second output of the PROM is to be used to select the memory module containing the operand to be referenced in the execution of the next instruction. This second output of the PROM is of a code size required to identify any one of the modules in the bank. The PROM has a third output that may be used to increment the location counter based upon the length of the next instruction. Where the second output of the PROM is not to be used to select the memory module containing the operand to be referenced, the first output of the PROM has a state such that it gates out information stored in a program status word register to identify the memory module containing the operand of the next instruction to be executed. To provide for direct CPU intervention in the execution of instructions, such as may occur in the case of an interrupt, prescribed bits of the CPU data bus may be selectively coupled to the module selection circuitry, so that the opcode-dependent operation of the PROM is bypassed and direct CPU selection within the memory bank may be achieved.

Lookahead memory address control system

A microprogrammed controller for interconnection between a central processor unit and at least one peripheral unit for controlling the transfer of data therebetween in response to instructions from the central processor unit provides for simplified bit manipulation through a feedback circuit which feeds the data to be supplied to the peripheral unit back to the input bus of the controller for further processing. In this way bit manipulation can be accomplished with a single microinstruction to provide for higher speed and efficiency of operation.

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Richardson, TX, United States of America

James O Rozell