Advanced Micro Devices Corporation

James O Mergard

Michael S Quimby

Dale E Gulick

Larry David Hewitt

James Raymond Magro

Pratik Mukundray Mehta

Asif Q Khan

Carl Kittredge Wakeland

Robert Paul Gittinger

An I/O node for a computer system including an integrated graphics engine and integrated I/O hub. An input/output node that is implemented on an integrated circuit chip includes a transceiver unit, a graphics engine and an I/O hub. The transceiver unit may receive and transmit packets on a point-to-point link of a packet interface. The graphics engine may be coupled to receive graphics packets received by the transceiver unit and may render digital image information in response to receiving the graphics packets. The I/O hub may be coupled to receive I/O packets corresponding to packets received by the transceiver unit and may initiate bus cycles corresponding to the I/O packets upon a peripheral bus. The packet interface link may be a point-to-point HyperTransport&#x2122; link including a first and second set of uni-directional wires which may convey control and data packets over the same wires.

I/O node for a computer system including an integrated graphics engine and an integrated I/O hub

An I/O node for a computer system including an integrated graphics engine. An input/output node is implemented upon an integrated circuit chip. The I/O node includes a first transceiver unit, a second transceiver unit, a packet tunnel, a graphics engine and a graphics interface. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus and the second transceiver unit may receive and transmit packet transactions on a second link. The packet tunnel may convey selected packet transactions between the first and the second transceiver unit. The graphics engine may receive graphics packet transactions from the first transceiver unit and may render digital image information in response to receiving the graphics transactions. The graphics interface may receive additional graphics packet transactions from the first transceiver unit and may translate the additional graphics packet transactions into transactions suitable for transmission upon a graphics bus.

I/O node for a computer system including an integrated graphics engine

A bus bridge mechanism is provided with an automatic delayed transaction enable mode. When the automatic delayed transaction enable mode is activated, a bus master making a read request is immediately signaled to retry the transaction, and the read request is treated by the bus bridge as a delayed read request to be completed asynchronously. The delayed read request, when completed, supplies data to the bus master on the next retry of the read request by the bus master following the completion of the delayed read request.

Automatic early PCI transaction retry

A flexible address mapping method and mechanism allows mapping regions of a microcontroller's memory and I/O address spaces for a variety of applications by defining memory regions which are mapped to one of a set of physical devices by a programmable address mapper controlled by a set of programmable address registers. The mapping allows setting attributes for a memory region to prohibit writes, caching, and code execution. A deterministic priority scheme allows memory regions to overlap, mapping addresses in overlapping regions to the device specified by the highest priority programmable address register.

Method and apparatus for overlapping programmable address regions

A microcontroller provides a flexible architecture to readily support both general embedded applications and communications applications. The microcontroller includes an embedded processor, a relatively low-speed general purpose peripheral bus controller, a relatively high-speed peripheral bus host bridge, a primary memory controller, and a secondary memory controller, each coupled to a processor bus. The general purpose peripheral bus controller is coupled to a relatively low-speed general purpose peripheral bus which is coupled to a plurality of integrated general purpose peripherals. The relatively high-speed peripheral bus host bridge is coupled to a relatively high-speed peripheral bus capable of supporting a plurality of communication-oriented peripherals. The secondary memory controller shares an address bus with the general purpose peripheral bus controller and shares a data bus with either the primary memory controller or the general purpose peripheral bus controller. The control timing of the secondary memory controller is independent of the control timing of the general purpose peripheral bus controller. Also, a processor arbiter is coupled to the embedded processor, and a relatively high-speed peripheral bus arbiter is coupled to the peripheral bus host bridge. Aside from the microcontroller, an embedded system can include a relatively low-speed general purpose peripheral bus and a relatively high-speed peripheral bus, both external to the microcontroller. The external relatively lowspeed general purpose bus can be coupled to the relatively low-speed general purpose peripheral bus controller, and the external relatively high-speed peripheral bus can be coupled to the relatively high-speed peripheral bus host bridge.

Flexible microcontroller architecture

A microcontroller for PC/AT-compatible or non-PC/AT compatible embedded environments is disclosed. The microcontroller includes a general purpose bus which may emulate an ISA bus in a PC/AT-compatible mode. PC/AT-compatible DMA channels, interrupt controllers, programmable timers, a real-time clock, processor, and a flexible memory and an I/O mapping scheme are provided by the microcontroller. The programmable timers, interrupt controllers, DMA channels and I/O mapping can be configured for a PC/AT-compatible mode or a non-PC/AT-compatible mode. In particular, the plurality of interrupt controllers are configured such that some are enabled during PC/AT-compatible operation while the remainder are disabled. The microcontroller further embeds several PC/AT peripheral devices and yet maintains the flexibility to support external devices if desired by the embedded system designer. Other PC/AT-compatible features are also supported by the microcontroller.

Flexible PC/AT-compatible microcontroller

A processor-based system such as a microcontroller supports a non-concurrent mode in which a bus master requesting ownership of a peripheral bus is forced to acquire ownership of both the peripheral bus and a processor bus. The system includes a peripheral bus arbiter to detect a peripheral bus request for the peripheral bus by a bus master, to generate a processor bus request for the processor bus in response to detecting the peripheral bus request, and to grant the bus master ownership of the peripheral bus if the bus master is granted ownership of the processor bus. The peripheral bus arbiter maintains ownership of the processor bus by the bus master until the bus master releases ownership of the peripheral bus. Similarly, a bus master seeking ownership of the processor bus can be forced to acquire ownership of the peripheral bus. The non-concurrent mode can be applied to various multi-bus architectures. One advantage of the non-concurrent mode is improved debug capability.

Method and apparatus for non-concurrent arbitration of multiple busses

A method and system is provided for avoiding data bus contention between EDO DRAM banks during a burst cycle to a memory page crossing a memory bank boundary. Each memory bank has output drivers configured to selectively drive data on a common data bus. The disclosed method and system contemplate decoding memory addresses into bank select signals and comparing the bank select signals for the current memory cycle to the state of the bank select signals in the previous cycle. If the current access is to a different bank, then the cycle is delayed and a disable signal is pulsed active to the EDO DRAM, disabling the output drivers. The memory page is kept open in the memory banks to allow bursts across bank boundaries. The current cycle is then allowed to continue to completion and data bus contention is avoiding while crossing the bank boundary.

Method and system for supporting non-deterministic burst lengths in a

A communication system is provided that includes a mechanism for selectively addressing memory banks depending upon the configuration of that system. The communication system can therefore operate in accordance with two possible modes of operation. According to a first mode, the local CPU can access one set of memory banks concurrent with an external device accessing the other set of memory banks. According to a second mode of operation, either the local CPU can access the memory banks or an external device can access the memory banks, one exclusive of the other. In one version of the second mode of operation, address signals to the memory banks can be physically connected leaving signals free to be used as general purpose input/output signals. The mechanism by which memory banks can be addressed and data transferred to and from those banks readily lends itself to communication applications to which the present system may be attributed.

Communication system which in a first mode supports concurrent memory

A computer system is provided including a CPU, a graphics controller, system memory, data steering logic, a DMA controller and arbitration logic. The graphics controller and system memory are coupled to a high-speed data bus. Data accessed by the CPU, the DMA controller and the graphics controller is all stored in the system memory. The data steering logic is also coupled to the high-speed data bus and to a low-speed data bus, and to the CPU. The data steering logic is configured to selectively couple the CPU to either the high-speed data bus or the low-speed data bus, thereby accommodating data transfers between the CPU and a bus device connected to the slow-speed data bus concurrent with data transfers between the graphics controller and the system memory. The data steering logic may also accommodate data transfers by the DMA controller on the slow-speed data bus concurrent with graphics controller data transfers. The arbitration logic arbitrates for access to the system memory between the CPU, DMA controller and graphics controller. In an alternative mode, the data steering logic accommodates data transfers between the CPU and the system memory over both the high-speed and slow-speed buses as a single double width high speed bus. The CPU, graphics controller, DMA controller, data steering logic and arbitration logic as described above may all be included within a single integrated circuit device along with various PC compatibility cores, thus achieving a low-cost, low-space system without sacrificing overall performance.

Computer system for concurrent data transferring between graphic

A DRAM control circuit accommodates different speed grade DRAMs by modifying the RAS strobe. A number of wait states are inserted into a DRAM access cycle, having a start time and an end time, between the start and the end time of the access cycle. When the number of wait states inserted is zero, the RAS is deasserted at a first time relative to the end of the access cycle. When the number of wait states is at least one, the RAS is deasserted at a second time, earlier than the first time, relative to the end time of the access cycle, thereby increasing the row address strobe precharge time.

Modifying RAS timing based on wait states to accommodate different speed

A communication system which includes more efficient bus utilization for higher data throughput. The communication system includes various logic devices connected to a system bus. The communication system intelligently utilizes unused system bus bandwidth for improved performance. The communication system includes a receive buffer, a memory, a central processing unit (CPU), a direct memory access (DMA) controller, and a bus arbiter each preferably coupled to the system bus. The buffer is operable to generate a low priority DMA transfer request when any amount of data is stored in the buffer. The buffer is also operable to generate a high priority DMA transfer request when a certain threshold or amount of data is stored in the buffer, i.e., when a certain 'water-level' has been reached. When the buffer generates the low priority DMA request, the DMA controller and/or bus determine if the system bus is otherwise not being utilized, e.g., if the CPU is currently operating out of its cache system and no other devices have requested or are using the bus. If so, the DMA transfers are allowed to proceed. The high priority DMA transfer request operates normally, guaranteeing access to the system bus to avoid FIFO overruns.

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Pflugerville, TX, United States of America

James O Mergard