Institute for the Development of Emerging Architectures, L.l.c.

Intel Corporation

Hewlett-packard Company

James O Hays

Jonathan Kent Ross

Stephen G Burger

Koichi Yamada

Gary N Hammond

William R Bryg

Rajiv Gupta

Sunil Saxena

Dale Calvin Morris

Jerome C Huck

John M Kessenich

Dean A Mulla

Nhon Toai Quach

Ralph Michael Kling

Sorin Iacobovici

Alberto J Munoz

Carol Linda Thompson

Jack D Mills

Stefan M Freudenberger

Valentin Anders

John W C Fu

Gary N Hammon

A computer system includes a processor for executing a program and an interruption handler from a memory. The processor includes an instruction pointer indicating a memory location of a current executing instruction. The processor executes a trampoline check instruction in the program which tests a condition and if the condition is true, causes an interruption and supplies an address displacement. The interruption handler responds to the interruption and restarts execution of the program at a restart point indicating a memory location of a special handler in the program. The restart point is a sum of the address displacement and a value of the instruction pointer at the time of the interruption. If the condition is false, normal control flow of the program is continued.

Emulated branch effected by trampoline mechanism

An uncorrectable error is detected in the data of a computer system. The erroneous data is allowed to be stored in first and second caches of the computer system while the system runs first and second processes, the first process being associated with the data. The first process is terminated when an attempt is made to load the data from the cache. Meanwhile, the second process continues to run.

Method and apparatus for handling data errors in a computer system

The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.

Apparatus and method for a virtual hashed page table

A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time. When a virtual-to-physical entry is established for a page in a region having an RID stored in a region register, the RID and VRN are stored in the appropriate fields of the TLB entry. In addition, the valid field is set and the rpV field is set to indicate that the TLB entry contains an active VRN-to-RID mapping, thereby pre-validating the region. When a physical address is translated into a virtual address, a VRN and a VPN are extracted from the virtual address and provided to the TLB. The TLB is searched to find an entry having a set valid field, a set rpV field, and VRN and VPN fields containing entries matching the VRN and VPN extracted from the virtual address. If such an entry is found, the protection and access attributes field is used to determine whether the requested access is allowed. If the requested access is allowed, the PPN from the PPN field of the TLB entry is combined with an offset from the virtual address to produce a physical address that is used to complete the memory access.

Method and apparatus for pre-validating regions in a virtual addressing scheme

A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A &ldquo;short format&rdquo; page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single &ldquo;long format&rdquo; page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address. If the computer system is operating with long format page tables, the next step is to form a hash index by combining the hash page number and the region identifier referenced by the region portion of the virtual address, and to form a table offset by shifting the hash index left by K bits, wherein each long format page table entry is 2 bytes long. However, if the computer system is operating with short format page tables, the next step is to form a hash index by setting the hash index equal to the hash page number, and to form a table offset by shifting the hash index left by L bits, wherein each short format page table entry is 2 bytes long. Next, a mask is formed based on the size of the page table. A first address portion is then formed using the base address of the page table and the mask, and a second address portion is formed using the table offset and the mask. Finally, the entry address is formed by combining the first and second address portions. By providing a single algorithm capable of generating a page table entry for both long and short format page tables, the present invention reduces the amount of logic required to access both page table formats, without significantly affecting execution speed.

Method and apparatus for calculating a page table index from a virtual address

A translation lookaside buffer (TLB) is provided including a first storage location in the TLB for storing at least a portion of a first virtual to physical memory translation. The first storage location in the TLB is both hardware-managed and software-managed. The TLB also includes a second storage location in the TLB for storing at least a portion of a second virtual to physical memory translation. The second storage location in the TLB is only software-managed.

Software and hardware-managed translation lookaside buffer

The inventive system and method allows for software control of hardware drral of exceptions in speculative operations, and comprises three components. The first component is processor stored information which reflects the code generation strategy of applications and is used by hardware and the operating system to control exception deferral. The second component is processor stored information set by the operating system to specify to hardware which type of faults should be automatically deferred. The third component is further processor stored information which indicates to the hardware to defer certain exception causing aspects of the speculative operation, while performing other non excepting aspects of the speculative operation. The stored information is set after the operating system exception handler has unsuccessfully attempted fault resolution.

Computer architecture for the deferral of exceptions on speculative

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San Jose, CA, United States of America

James O Hays