Texas Instruments Corporation

James O Bondi

Jonathan H Shiell

Donald Edward Steiss

John M Johnsen

Ashwini K Nanda

Joel J Graber

Simonjit Dutta

In a computer system ( ) embodiment, there is included a memory ( ) and circuitry ( ) for prefetching information from the memory in response to a prefetch request. The system further includes a system resource ( ), wherein the system resource is burdened in response to a prefetch operation by the circuitry for prefetching information. The system resource is also further burdened in response to other circuitry ( ) using the system resource. The system further includes circuitry ( ) for determining a measure of the burden on the system resource. Lastly, the system includes circuitry ( ) for prohibiting prefetching of the information by the circuitry for prefetching information responsive to a comparison of the measure of the burden with a threshold. Other circuits, systems, and methods are also disclosed and claimed.

Microprocessor circuits, systems, and methods for conditioning information prefetching based on resource burden

In a computer system (,) embodiment, there is included a memory (,) and circuitry (,) for prefetching information from the memory in response to a prefetch request. The system further includes a system resource (,), wherein the system resource is burdened in response to a prefetch operation by the circuitry for prefetching information. The system resource is also further burdened in response to other circuitry (,) using the system resource. The system further includes circuitry (,) for determining a measure of the burden on the system resource. Lastly, the system includes circuitry (,) for prohibiting prefetching of the information by the circuitry for prefetching information responsive to a comparison of the measure of the burden with a threshold. Other circuits, systems, and methods are also disclosed and claimed.

Microprocessor circuits, systems and methods for conditioning information prefetching based on resource burden

A microprocessor (10) and corresponding system (300) is disclosed in which prefetch of instruction or data from higher level memory (11; 307; 305) may be performed in combination with a fetch from a lower level cache (16). A branch target buffer (56) has a plurality of entries (63) associated with branching instructions; in addition to the tag field (TAG) and target field (TARGET), each entry (63) includes prefetch fields (PF0 ADDR; PF1 ADDR) containing the addresses of memory prefetches that are to be performed in combination with the fetch of the branch target address. Graduation queue and tag check circuitry (27) is provided to update the contents of the prefetch fields (PF0 ADDR; PF1 ADDR) by interrogating instructions that are executed following the associated branching instruction to detect instructions that involve cache misses, in particular the target of the next later branching instruction.

Combined branch prediction and cache prefetch in a microprocessor

A microprocessor (10) operating in response to a clock signal (CLK) having a clock period. The microprocessor includes a readable memory (16), and this readable memory stores code (BIST) for performing diagnostic evaluations of the microprocessor. The diagnostic evaluations include a first evaluation to occur under non-failure operation at a first clock period (24) and a last evaluation to occur under non-failure operation at a last clock period (26). The microprocessor further includes circuitry (14) for issuing a series of addresses to the readable memory in order to address the code for performing diagnostic evaluations of the microprocessor. Still further, the microprocessor includes a conductor (D0) externally accessible and for providing a signal from the microprocessor. Lastly, the microprocessor includes circuitry (12) for outputting a diagnostic signal on the externally accessible conductor during performance of the diagnostic evaluations. Given the externally accessible conductor, divergence of the diagnostic signal from a predetermined pattern before the last dock period indicates a failure of the diagnostic evaluations before the last clock period.

Circuits, systems, and methods for external evaluation of microprocessor

A circuit (10) for producing a microprogram memory address (16). This circuit includes circuitry (18I, 18J) for selecting a plurality of condition codes. Additionally, the circuit includes logic circuitry (20) for producing a result by performing logic operations using as operands the selected plurality of condition codes. The result of the logic operations forms a first portion (LSB', or LSB' and NLSB') of the microprogram memory address.

Microprocessor with reduced microcode space requirements due to improved

A microprocessor comprising an instruction pipeline (36) comprising a plurality of successive instruction stages. An instruction passes from a beginning stage (38), through a plurality of intermediary stages (40 through 52), and to an ending stage (54) of the plurality of successive instruction stages. The microprocessor also comprises a storage circuit (58) coupled to receive program thread information output from a first stage (48) of the intermediary stages. Still further, the microprocessor comprises selection circuitry (56) comprising a first input, a second input, and an output for outputting output information from its first and second inputs. The first input of the selection circuitry is coupled to receive output information output from the first stage. The second input of the selection circuitry is coupled to receive program thread information output from the storage circuit. The output of the multiplexer is coupled to an input of a second stage (50) of the intermediary stages, wherein the second stage follows the first stage. Other circuits, systems, and methods are also disclosed and claimed.

Pipelined microprocessor with branch misprediction cache circuits,

Circuits, systems, and methods relating to processor which processes a plurality of sequentially arranged instructions. In the method, one method step (10) receives into a processor pipeline an instruction from the plurality of sequentially arranged instructions. Another step (12) determines whether the received instruction comprises a short forward branch instruction. If the received instruction comprises a short forward branch instruction, the method (14) issues a detection signal and (16) issues a condition signal representing whether or not the condition of the short forward branch instruction is satisfied. Continuing, the method (18) receives into the processor pipeline a first group of instructions of the plurality of sequentially arranged instructions, where each is between the short forward branch instruction and the target instruction. Each such instruction passes fully through the processor pipeline and the method (26) suppresses its result in response to the detection signal if the condition signal represents that the condition of the short forward branch is satisfied.

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Plano, TX, United States of America

James O Bondi