Texas Instruments Corporation

James Nodar

Hong Jiang

Bryan E Bloodworth

Paul Merle Emerson

Ashish Manjrekar

A circuit ( ) and method are provided for generating a signal ( ) indicating an open impedance fault of a coil ( ) of a write head ( ) of a mass data storage device ( ). The circuit ( ) includes a differential amplifier ( ) with the electrical component ( ) being connected as a load in a first leg thereof. An impedance element ( ) is provided in a second leg of the differential amplifier ( ), and a pair of bipolar transistors ( ) are respectively connected in the first and second legs. The pair of bipolar transistors ( ) have a constant bias voltage (Bias) applied to inputs thereof, and an output circuit is connected to an output node of the first leg of the differential amplifier ( ).

Write head fault detection with small threshold

The present invention provides an apparatus, system and method of improving the bias response time for pre-amplifier circuits which utilize noise reduction capacitors . The system uses a quick recovery circuit electrically connected to the capacitive node of the pre-amplifier circuit. The quick recovery circuit comprises a gain amplifier with a resistive input and a controlled current source . The controlled current source corresponds to adjustments in a controlled current source of the pre-amplifier and is electrically connected to the resistive input of the gain amplifier . The gain amplifier can be selectively switched to operatively connect an output to the capacitive node of the pre-amplifier circuit.

Capacitor bias recovery methodology

A circuit for the Class-A differential amplification of two input signals. A first constant current source 22 is connected between a voltage supply terminal 3 and a node 8. A second constant current source 24 is connected between the supply terminal 3 and a node 9. A first transistor T1, with a control electrode connected to input terminal 1, has a conduction path connected between node 8 and a voltage supply terminal 10. A second transistor T2, with a control electrode connected to input terminal 2, has a conduction path connected between node 9 and terminal 10. A third transistor T3, with a control electrode connected to input terminal 1, has a conduction path connected between node 9 and an output terminal 6. Finally, a fourth transistor T4, with a control electrode connected to input terminal 2, has a conduction path connected between node 8 and an output terminal 7.

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Dallas, TX, United States of America

James Nodar