Cray Research, Inc.

Unisys Corporation

James N Kruchowski

Melvin C August

Eugene F Neumann

Stephen E Nelson

Richard R Steitz

Lloyd T Shepherd

John B Eder

Robert K Sakurai

A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by 'opening' the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

Integrated circuit chip carrier lid

The present invention provides an improved method for manufacturing circuit boards with high power, high density interconnects. Printed circuit board technology, integrated circuit technology, and heavy-build electroless plating are combined to produce multilayer circuit boards comprised of substrates with different interconnect densities. In the higher density substrates, thick metallized layers are built-up by combining additive and subtractive techniques. These thicker foils minimize DC voltage drop so that conductors can run for longer distances. The conductors are substantially more square than their thin film equivalents, thus providing better performance for high frequency signals. Power distribution capabilities are enhanced by the present invention, so that circuit boards fully populated with dense, high-speed, high-power integrated circuits can easily be supplied with their necessary power requirements.

High power, high density interconnect apparatus for integrated circuits

Apparatus and method for determining the electrical length of a signal flow path, such as a twisted-pair conductor, to create conductors of the same electrical length are disclosed. The term electrical length refers to a certain physical distance for a length of conductor for which an electrical signal travels, or propagates along the conductor, in a specified amount of time. The apparatus preferably includes a Time Domain Reflectometer 25 (including pulse generator means 30 and electrical response display means 20) which is cooperatively connected to a first end of a conductor pair 51 under test. The conductor pair 51 is inserted through a ground plane 60 or other impedance changing device. Means to mark or cut 62 the conductor 51 are located within the ground plane 60 or as close as possible to the point at which the impedance is changed. Processing means 40 are utilized to adjust the conductor 51 length relative to the ground plane 60. In operation, the pulse generator means 30 sends a pulse along the conductor 51. The ground plane 60 reflects a portion of the pulse back to the electrical response display means 20 with the signal propagation delay per unit mechanical length being calculated thereby.

Method and apparatus for optimizing the electrical length of a signal

The present invention provides an improved method for manufacturing circuit boards with high power, high density interconnects. Printed circuit board technology, integrated circuit technology, and heavy-build electroless plating are combined to produce multilayer circuit boards comprised of substrates with different interconnect densities. In the higher density substrates, thick metallized layers are built-up by combining additive and subtractive technique. These thicker foils minimize DC voltage drop so that conductors can run for longer distances. The conductors are substantially more square than their thin film equivalents, thus providing better performance for high frequency signals. Power distribution capabilities are enhanced by the present invention, so that circuit boards fully populated with dense, high-speed, high-power integrated circuits can easily be supplied with their necessary power requirements.

High power, high density interconnect method and apparatus for

A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by 'operating' the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

Chip carrier with terminating resistive elements

Method of making a chip carrier with terminating resistive elements

A fixture is provided which cleans a plasma etcher of a type that has a holding member with a surface which holds wafers that are to be etched, and an enclosing member which encloses the holding member to form a chamber for the plasma. This fixture operates to produce a large voltage change near the enclosing member and thereby enable the cleaning of the enclosing member by the plasma itself. To achieve such a large voltage change, the fixture is configured to fit inside of the enclosing member, provide a surface which is substantially larger than the surface of the holding member, and make electrical contact with the surface of the holding member. Preferably, the surface provided by the fixture is at least 50% larger than the surface of the holding member.

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Eau Claire, WI, United States of America

James N Kruchowski