Advanced Micro Devices Corporation

James Mossman

Anthony J Bybell

Robert Bradford Cohen

Sudherssen Kalaiselvan

Tzu-Wei Lin

A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.

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Santa Clara, CA, United States of America

James Mossman