International Telephone and Telegraph Corporation

James Monroe Clark

Stuart Barry Cohen

Arthur Howard Magnus

Bead seal gasket

There is disclosed apparatus for keeping two or more distinct groups of data separate from each other within a processor based system. The system employs at least two system areas, where one system area is assigned to have higher priority data than the other. By detecting the priority of a data operation, the lower priority system area is prevented by means of gates from having high priority data written into the lower priority system area. The higher priority system area can read data from the lower priority system area at all times and the lower priority system area can write data into the higher priority system area at all times.

Plural storage areas with different priorities in a processor system

Each of first N flip-flop stages, where N is an integer greater than one, has steered thereto an appropriate one of N bits of the data to be transmitted by a transmit write counter and a first N stage decoder under control of a transmit write clock. A transmit read counter under control of a transmit read clock steers the stored bits to a transmit data bus by means of a first multiplexer and first logic circuitry under control of a transmit read counter and a transmit channel timing signal. Each of second N flip-flop stages has steered thereto an appropriate one of N bits of received data by a receive write counter and a second N stage decoder under control of a receive write clock. A receive read counter under control of a receive read clock steers the stored bits to a receive data bus by means of a second multiplexer and second logic circuitry under control of the receive read counter.

Transmit and receive digital data channel elastic store

The phasing circuit transfers digital data from an external interface circuit to an internal interface circuit with no bit errors and no violation of bit count integrity under control of an external clock having a given frequency and a given phase and an internal clock having a frequency equal to the given frequency and a phase that is different than the given phase. The phasing circuit includes a data output from the external interface circuit, a first clock output to couple the external clock from the external interface circuit, a data input to the internal interface circuit, at least a second clock output to couple the internal clock from the internal interface circuit, at least first and second D-type flip flops having their D inputs and Q outputs coupled in cascade with each other, the data output and the data input and logic circuitry coupled to the clock input of each of the first and second flip flops, the second clock output and a selected one of the data output and the first clock output to select the internal clock or an inverted version of the internal clock as the clock for the first flip flop to provide the desired digital data transfer.

Automatic phasing circuit to transfer digital data from an external

Two D-type flip flops have a clock and a 1/4-bit delayed clock coupled to the D inputs of respective ones of the two flip flops to provide a +/- phase error of a present sample of digital data coupled to the clock inputs of the two flip flops and a second signal indicating a large/small phase error of the present sample of the data. A third signal indicating a +/- phase error of a previous state of the data is provided and a fourth signal indicating a large/small error of the previous state of the data is provided. A read only memory is responsive to the first, second, third and fourth signals in accordance with a given set of rules to produce a phase error signal with a clockwise change of phase states of the data providing a negative frequency error signal and a counter-clockwise change of phase states of the data providing a positive frequency error signal.

Digital phase/frequency comparator

A first generator provides a reference pulse train having a predetermined reference frequency. A second generator including a voltage controlled oscillator provides a bit clock having a repetition frequency locked to the repetition frequency of the bits of digital data. A first divider coupled to the first generator divides the reference frequency by a selected one of a first division factor and a second division factor different than the first division factor. A fourth divider coupled to the second generator divides the repetition frequency of the bit clock by a selected one of a third division factor and a fourth division factor different than the first, second and third division factors. A phase comparator coupled to the first and second dividers compare the phase of the output signals of the first and second dividers and produces a control signal proportional to the phase difference between the output signals of the first and second dividers. The control signal is coupled through a loop filter to the voltage controlled oscillator to lock the phase of the bit clock to the bits of the digital data. Logic circuitry coupled to the digital data source, the second generator and the first and second dividers produce a phase slip rate signal to select the appropriate one of the first and second division factors for the first divider and to select the appropriate one of the third and fourth division factors for the second divider.

Digital double differential phase-locked loop

The demodulator produces an inphase digital reference signal having the form cos A by means of an analog-to-digital converter and a quadrature digital reference signal having the form sin A by means of an N-stage shift register coupled to the converter. An inphase digital FSK signal having the form cos B is provided by a second analog-to-digital converter and a quadrature digital FSK signal having the form sin B is produced by a second N-stage shift register. A first read only memory responsive to the inphase and quadrature digital reference signals and the inphase and quadrature FSK signals produce an inphase code signal and a quadrature code signal for estimating the value of (B - A). A first M-stage shift register delays the inphase code signal and a second M-stage shift register delays the quadrature code signal. A second read only memory responsive to the inphase and quadrature code signals and the delayed inphase and quadrature code signals determine whether the value of (B - A) is increasing or decreasing. Logic gate means coupled to the two outputs of the second read only memory determines whether a first given code is detected more frequently than a second code and vice versa. A low pass filter coupled to the logic gate means averages the difference between the first and second given codes to produce a high voltage for a 'mark' and a low voltage for a 'space.'

Digital FSK demodulator

An asynchronous digital time division multiplexer and demultiplexer combination at one communication terminal is disclosed that will multiplex first N asynchronous source data signals having a first mixture of different bit rates into a transmitted synchronous data stream having a predetermined fixed data format and a given bit rate greater than the total of the bit rates of the source data and to demultiplex second N asynchronous source data signals having a second mixture of different bit rates from a received synchronous data stream having the predetermined fixed data format and the given bit rate. The combination includes an automatic channel assignment circuit to assign channels of the two data streams to the asynchronous source data signals in a manner to minimize temporary data memory regardless of the number of different bit rates by assigning the data signals to channels of the associated one of the two data streams so that the bits of each of the data signals tend to have equal spacing throughout the bits of the associated one of the two data streams. The channel assignment control circuit also includes a means to automatically indicate when the total of the mixture of bit rates has exceeded an allowable maximum.

Asynchronous multiplexer and demultiplexer combination

An automatic channel assignment circuit in a controlling association with an asynchronous or synchronous digital time division multiplexer and demultiplexer combination at one communication terminal to assign channels of transmitted and received synchronous data streams to asynchronous or synchronous source data signals in a manner to minimize temporary data memory regardless of the number of different bit rates of the source data signals by assigning the data signals to channels of the associated one of the transmitted and received data streams so that the bits of each of the data signals tend to have equal spacing throughout the bits of the associated one of the transmitted and received data streams. Each of the transmitted and received data streams have a predetermined fixed data format with respect to the channels and a given bit rate greater than the total of the bit rates of the source signals. However, the automatic channel assignment circuit provides, in effect, an automatically determined-at-the-time-of-rate-selection a variable data format with respect to the ports. The channel assignment control circuit also includes a means to automatically indicate when the total of the mixture of bit rates has exceeded an allowable maximum.

Automatic channel assignment circuit

A transmit phase locked loop receives data to be transmitted having a bit rate equal to a first given one of a predetermined number of different bit rates. A diphase demodulator responds to the transmit phase locked loop and the data to be transmitted to provide output data for transmission. A receive write timing signal and a receive read timing signal is coupled to a receive phase locked loop to compare the phase relation of the two timing signals. A diphase modulator responds to received data having a bit rate equal to a second given one of the predetermined number of different bit rates and a clock signal provided by the receive phase locked loop to provide output data for utilization. The first given one of different bit rates and the second given one of different bit rates may have equal or different bit rates.

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Cedar Grove, NJ, United States of America

James Monroe Clark