Intel Corporation

James Mitchell

Mark Sullivan

Kimberly A Davis

Patrick A Themins

Malay Trivedi

David K Vavro

Amit Kumar Srivastava

Janusz Jurski

David N Lombard

Chih-Cheh Chen

Piotr Michael Kwidzinski

Chung-Chi Wang

Michael J Karas

Syed Z Islam

Divya Gupta

Christopher L Chappell

Panakaj Kumar

In one embodiment, an apparatus includes: a plurality of cores to execute instructions; a firmware agent to execute a first firmware; a Peripheral Component Interconnect Express (PCIe) interface to communicate with a device via a PCIe link; and a boot agent coupled to the PCIe interface to download the PCIe firmware from a non-volatile memory and provide the PCIe firmware to the PCIe interface. The PCIe interface may receive a PCIe firmware for the PCIe interface before the firmware agent is to receive the first firmware. Other embodiments are described and claimed.

Systems, apparatus and methods for rapid peripheral component interconnect express (PCIE) system boot

An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.

Dynamic lane access switching between PCIe root spaces

A dual host system and method with back to back non-transparent bridges and a proxy packet generating mechanism. The proxy packet generating mechanism enables the hosts to send interrupt generating packets to each other.

Method and apparatus to facilitate system to system protocol exchange in back to back non-transparent bridges

A method and apparatus to use Solid State Drives (SSD) in a high availability enterprise system is provided. Concurrent redundant paths are provided to the SSD to at least two storage controllers via a serial system bus using a non-storage bus protocol.

Method and apparatus to provide a high availability solid state drive

Methods and apparatus, including computer program products, implementing techniques for forming an Advanced Switching (AS) packet by applying AS path binding information to a packet received over a Peripheral Component Interconnect-Express (PCIe) fabric according to a downstream port identifier associated with the packet, and sending the AS packet to an AS fabric. Methods and apparatus, including computer program products, implementing techniques for processing an AS packet received over an AS fabric by comparing an AS payload of the AS packet with one or more memory spaces associated with port identifiers, determining whether the AS payload comprises a base packet to be transmitted to the PCIe fabric based on the comparison, and if so, removing an AS header from the AS packet to reveal the base packet.

Packet processing in switched fabric networks

A digital signal processor uses a number of independent sub-processors that may be controlled by a master programmable controller. For example, a specialized input processor may process input signals while a specialized output processor may process output signals. Each of these processors may also accomplish math functions when input and output processing is not necessary. The various processors may communicate with one another through general purpose registers which receive data and provide data to any of the processors in the system. Math processors may be added as needed to accomplish desired mathematical functions. In addition, a RAM processor may be utilized to hold the results of intermediate calculations in one embodiment of the present invention. In this way, an adaptable and scaleable design may be implemented that accommodates a variety of different operations without requiring redesign of all the components.

Digital signal processor having a plurality of independent dedicated processors

In one embodiment, the present invention includes a method for selecting first data received in a first die of a multi-chip package (MCP) from a second die of the MCP via an intra-package link for output from a selector during a first clock period of a first clock signal, selecting second data transmitted from the second die to the first die for output from the selector during a second clock period, and transmitting the first and second data from the MCP via an external link. Other embodiments are described and claimed.

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Chandler, AZ, United States of America

James Mitchell