Sun Microsystems, Inc.

Altera Corporation

James Michael O'Connor

Marc R Tremblay

William N Joy

Sanjay Vishin

Guy Lewis Steele, Jr

Ole Agesen

Steven K Heller

Derek R White

Edward D Funnekotter

Shailender Chaudhry

Daniel Dwight Grove

Jonathan Lockwood Huie

Jon Huie

Sudheendra Hangal

A high performance network address processor is provided comprising a longest prefix match lookup engine for receiving a request for data from a designated network destination address. An associated data engine is also provided to couple to the longest prefix match lookup engine for receiving a longest prefix match lookup engine output address from the longest prefix match lookup engine and providing a network address processor data output corresponding to the designated network destination address requested. The high performance network address processor longest prefix match lookup engine comprises a plurality of pipelined lookup tables. Each table provides an index to a given row within the next higher stage lookup table, wherein the last stage, or the last table, in the set of tables comprises an associated data pointer provided as input to the associated data engine. The associated data engine also comprising one or more tables, the associated data engine generating a designated data output associated with the designated network address provided to the high performance NAP.

High performance network address processor system

The present invention provides the method and system that redistribute the nodes of a sorted tree to enable faster data insertion. Further, the tree typically contains a fixed number of levels, each comprising a fixed number of nodes. Each node in the tree is indexed and each leaf node may comprise a number of data segments. An increment is empirically calculated as space redistributed among non-empty leaf nodes. Furthermore, when a data segment is inserted and certain conditions are met, a data structure with a marked head and tail effectively 'traverses' the tree from one end to the other searching for empty leaf nodes. In cases where the data structure encounters an empty leaf node, the data structure continues traversing unless empirically determined conditions stipulate that the process halts until the next data segment insertion before continuing. Moreover, in cases where the data structure encounters a non-empty leaf node, the contents of the node are copied from the head to the tail of the data structure. When the node has been copied, the data structure updates the tree to ensure that a lookup operation on the copied node remains valid and that the invariants of the tree hold before and after the redistribution. Furthermore, the contents in the head of the data structure are then deleted and the tail advanced to leave an increment amount of empty spaces in the traveling direction. The traversal process may then follow one of two possible paths of action: either continue traversing the tree or halt for the next data insertion before continuing.

Method and system for rapid insertion of various data streams into sorted tree structures

An embodiment of the present invention described and shown in the specification and drawing is a Ternary Content Addressable Memory (TCAM) multi-dimensional multi-way branch selector. The embodiment that is disclosed includes a wide TCAM and a pre-TCAM multi-field multi-mode comparator for coupling to a microprocessor for performing multi-way branching decisions based on multi-dimensional comparisons. It is emphasized that this abstract is provided to comply with the rule requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Ternary content addressable memory based multi-dimensional multi-way branch selector and method of operating same

A method and system for accurately validating performance and functionality of a processor in a timely manner is provided. First, a program is executed on a high level simulator of the processor. Next, a plurality of checkpoints are established. Then, state data at each of the checkpoints is saved. Finally, the program is run on a plurality of low level simulators of the processor in parallel, where each of the low level simulators is started at a corresponding checkpoint with corresponding state data associated with the corresponding checkpoint.

System and method for validating processor performance and functionality

A dual instruction set processor can decode and execute both code received from a network and other code supplied from a local memory. Thus, the dual instruction set processor is capable of executing two different types of instructions, from two different sources, permitting the dual instruction set processor to have maximum efficiency. A computer system with the foregoing described dual instruction set processor, a local memory, and a communication interface device, such as a modem, for connection to a network, such as the Internet or an intranet, can be optimized to execute, for example, JAVA code from the network, and to execute non-JAVA code stored locally, or on the network but in a trusted environment or an authorized environment.

Method frame storage using multiple memory circuits

A memory architecture in accordance with an embodiment of the present invention improves the speed of method invocation. Specifically, method frames of method calls are stored in two different memory circuits. The first memory circuit stores the execution environment of each method call, and the second memory circuit stores parameters, variables or operands of the method calls. In one embodiment the execution environment includes a return program counter, a return frame, a return constant pool, a current method vector, and a current monitor address. In some embodiments, the memory circuits are stacks; therefore, the stack management unit to cache can be used to cache either or both memory circuits. The stack management unit can include a stack cache to accelerate data transfers between a stack-based computing system and the stacks. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit includes a fill control unit and a spill control unit. Since the vast majority of memory accesses to the stack occur at or near the top of the stack, the dribble manager unit maintains the top portion of the stack in the stack cache. When the stack-based computing system is popping data off of the stack and a fill condition occurs, the fill control unit transfer data from the stack to the bottom of the stack cache to maintain the top portion of the stack in the stack cache. Typically, a fill condition occurs as the stack cache becomes empty and a spill condition occurs as the stack cache becomes full.

A computer processor includes a number of register pairs LOCKADD/LOCKCOUNT to hold values identifying when a computer resource is locked. The LOCKCOUNT register is incremented or decremented in response to lock or unlock instructions, respectively. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. In embodiments without LOCKOUT registers, the lock may be freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header in which two header LSBs store: (1) a LOCK bit indicating whether the object is locked, and (2) a WANT bit indicating whether a thread is waiting to acquire a lock for the object.

Locking of computer resources

The present invention provides a method and apparatus for executing a boundary check instruction that provides accelerated bound checking. The instruction can be used to determine whether an array address represents a null pointer, and whether an array index is less than zero or greater than the size of the array. Three extensions of a boundary check instruction are provided, with each performing a different combination of three boundary check comparisons. One comparison compares a first operand, which may contain the base address of an array, to zero. Another comparison evaluates the value of a second operand, which may contain an index offset, to determine if it is less than zero. The other comparison evaluates whether the value of the second operand is greater than or equal to a third operand. The third operand may indicate the size of an array. A trap is generated if any of the comparisons evaluates to true.

Array access boundary check by executing BNDCHK instruction with comparison specifiers

A memory architecture in accordance with an embodiment of the present invention improves the speed of method invocation. Specifically, method frames of method calls are stored in two different memory circuits. The first memory circuit stores the execution environment of each method call, and the second memory circuit stores parameters, variables or operands of the method calls. In one embodiment the execution environment includes a return program counter, a return frame, a return constant pool, a current method vector, and a current monitor address. In some embodiments, the memory circuits are stacks; therefore, the stack management unit to cache can be used to cache either or both memory circuits. The stack management unit can include a stack cache to accelerate data transfers between a stack-based computing system and the stacks. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control. The dribble manager unit include fill control it and a spill control unit. Since the vast majority of memory accesses to the stack occur at or near the top of the stack, the dribble manager unit maintains the top portion of the stack in the stack cache. When the stack-based computing system is popping data off of the stack and a fill condition occurs, the fill control unit transfer data from the stack to the bottom of the stack cache to maintain the top portion of the stack in the stack cache. Typically, a fill condition occurs as the stack cache becomes empty and a spill condition occurs as the stack cache becomes full.

A computer processor includes a number of register pairs LOCKADDR/LOCKCOUNT. In each pair, the LOCKADDR/LOCKCOUNT register is to hold a value that identifies a lock for a computer resource. When a lock instruction issues, the corresponding LOCKCOUNT register is incremented. When an unlock instruction issues, the corresponding LOCKCOUNT register is decremented. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. This scheme provides fast locking and unlocking in many frequently occurring situations. In some embodiments, the LOCKCOUNT registers are omitted, and the lock is freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header which includes a pointer to a class structure. The class structure is aligned on a 4-byte boundary, and therefore two LSBs of the pointer to the class structure are zero and are not stored in the header. Instead, two header LSBs store: (1) a LOCK bit indicating whether the object is locked, and (2) a WANT bit indicating whether a thread is waiting to acquire a lock for the object.

One embodiment of the present invention provides a system that enforces dependencies between memory references within a load store unit (LSU) in a processor. When a write request is received in the load store unit, the write request is loaded into a store buffer in the LSU. The write request may include a &ldquo;watch address&rdquo; specifying that a subsequent load from the watch address cannot occur before the write request completes. Note that the watch address is not necessarily the same as the destination address of the write operation. When a read request is received in the load store unit, the read request is loaded into a load buffer of the LSU. The system determines if the read request is directed to the same address as a matching watch address in the store buffer. If so, the system waits for the write request associated with the matching watch address to complete before completing the read request. In one embodiment of the present invention, if the read request is directed to the same address as a matching write request in the store buffer, the system completes the read request by returning a data value contained in the matching write request without going out to memory. In one embodiment of the present invention, the system provides an executable code write instruction that specifies the watch address.

Method and apparatus for enforcing memory reference dependencies through a load store unit

Elimination of traps and atomics in thread synchronization is provided. In one embodiment, a processor includes a lock cache. The lock cache holds a value that corresponds to or identifies a computer resource only if a current thread executing on the processor owns the computer resource. A lock cache operation (e.g., a lockcachecheck instruction) determines whether a value identifying a computer resource is cached in the lock cache and returns a first predetermined value if the value identifying the computer resource is cached in the lock cache. Otherwise, a second predetermined value is returned.

Elimination of traps and atomics in thread synchronization

The present invention provides a unique multi stack memory system to provide access to multiple portions of the method frames of a stack based computing system. In one embodiment of the invention, a multi-stack memory system includes a first stack configured to store a first frame component of a first method frame and a second frame component of a second method frame. A second stack is configured to store a second frame component of the first method frame and a first frame component of second method frame. The first frame component of the method frames can be for example an operand stack. The second frame components of the method frames can be, for example, arguments and local variable areas.

Multi-stack memory architecture

In executing a new method, a hardware processor loads the execution environment on a stack in the background and indicates what portion of the execution environment has been loaded so far, e.g., simple one bit scoreboarding. Thus, the hardware processor tracks the information in the execution environment loaded on the stack. The hardware processor tries to execute the bytecodes of the called method as soon as possible, even though the stack is not completely loaded. If accesses are made to variables already loaded, overlapping of execution with loading of the stack is achieved. Thus, execution and loading continue until information in the execution environment needed for the execution is not on said stack as indicated by said tracking.

Growing community of inventors

Union City, CA, United States of America

James Michael O'Connor