Carrier Access Corporation

James Michael Dougherty

Roger L Koenig

Gordon K Francis

Matthew D Morris

Brian Edward Angliss

Tim P Groth

A technique for performing a time slot interchange in a processor. The TSI process is surrounded by a multiplexing/demultiplexing circuit for converting a plurality of PCM highways into a single input serial data stream. The mux/demux circuit includes elastic stores to align frames and shift resisters to mux/demux with a minimum of delay. The TSI processor includes an input and an output buffered series port, a pair of input buffers, one to receive even-numbered frames from the PCM highways and one to receive odd-numbered frames, and an output buffer. Data is read from the appropriate input buffer in a non-sequential fashion as commanded by the processor in accordance with information stored in connection arrays (address buffers). The data is then written to the output buffer sequentially. The timing of the reading and writing steps is optimized relative to free running buffered serial port pointers for each BSP to reduce the frame delay.

Processor-based voice and data time slot interchange system

Customer services terminal input connected between telephone exchange and outputs. Interface circuits provide service between input and outputs Test means applies test conditions to interface circuits and/or to outputs associated with the interface circuits, and/or to ring/tip pairs associated with interface circuits, and/or to telephone lines associated with interface circuits Other interface circuits service input to other outputs Test means analog-to-digital converter includes reference input, analog measuring input, ground potential input, and test output Normally de-energized calibration relay has normally-closed switches and normally-open switches. Normally-closed switch connects reference voltage to reference input. Another normally-closed switch connects analog measuring input to test means generated voltage. Calibration switching means energizes calibration relay to connect analog measuring input to reference voltage via normally-open switch, to connect reference input to source of ground potential via another normally-open switch to generate calibration output useful for determining test results output when calibration relay is de-energized.

Customer services terminal method and apparatus for testing a plurality of interface circuits and telephone lines that are connected thereto

A telecommunications system includes a telephone exchange and a customer services terminal whose input is connected to the telephone exchange, and whose plural outputs are individually connected to one of a plurality of telephone lines. A plurality of interface circuits within the customer services terminal are individually connected intermediate the input and one of the plural outputs. Self-test means provides for the testing of selected interface circuits. Loop-test means provides for the testing of selected telephone lines. A self-test relay is responsive to the self-test means and operates to disconnect the selected outputs from corresponding telephone lines as self-test conditions are applied to selected interface circuits as these interface circuits are disconnected from the selected telephone lines. The loop test means applies loop-test conditions to selected interface circuits, while the selected interface circuits and the corresponding outputs remain connected to the corresponding telephone lines. In either case, other interface circuits, outputs, and telephone lines that are not undergoing test remain operative to supply telecommunications services between the telephone exchange and these other telephone lines.

Method and apparatus for self-testing a customer services terminal and for loop testing telephone lines that are connected thereto

A technique for performing a time slot interchange in a processor. The TSI process is surrounded by a multiplexing/demultiplexing circuit for converting a plurality of PCM highways into a single input serial data stream. The mux/demux circuit includes elastic stores to align frames and shift resisters to mux/demux with a minimum of delay. The TSI processor includes an input and an output buffered serial port, a pair of input buffers, one to receive even-numbered frames from the PCM highways and one to receive odd-numbered frames, and an output buffer. Data is read from the appropriate input buffer in a non-sequential fashion as commanded by the processor in accordance with information stored in connection arrays (address buffers). The data is then written to the output buffer sequentially. The timing of the reading and writing steps is optimized relative to free running buffered serial port pointers for each BSP to reduce the frame delay.

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Highlands Ranch, CO, United States of America

James Michael Dougherty